Node synchronization for multi-processor computer systems
View Patent ↗A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.
1. A method of controlling access by a set of accessing nodes to shared memory of a home node, the home node and accessing nodes being part of a multi-node shared-memory computer system, the method comprising:
determining that each node in the set of nodes has accessed the shared memory; and
forwarding a completion message to each node in the set of nodes after it is determined that each node has accessed the shared memory, the completion message having data indicating that each node in the set of nodes has accessed the shared memory of the home node.
2. The method as defined by claim 1 wherein determining comprises:
setting a synchronization variable to an initial value;
updating the synchronization variable each time one of the set of nodes accesses the shared memory of the home node; and
after updating the synchronization variable, determining if the synchronization variable and a test variable satisfy a prescribed mathematical relationship.
3. The method as defined by claim 2 further comprising:
determining that the synchronization variable satisfies the prescribed mathematical relationship with the test variable before forwarding the completion message.
4. The method as defined by claim 3 wherein the synchronization variable satisfies the prescribed mathematical relationship with the test variable when both variables have equal values.
5. The method as defined by claim 1 wherein forwarding comprises broadcasting the completion message to each accessing node in the set.
6. The method as defined by claim 1 wherein each accessing node in the set of nodes is synchronized to execute a set of steps of a common process, each accessing node not executing a subsequent step in the common process until receipt of the completion message.
7. The method as defined by claim 1 further comprising:
detecting that each node in the set of accessing nodes is to access the shared memory of the home node.
8. The method as defined by claim 1 wherein each accessing node repeatedly accesses its local memory to determine the value of a local synchronization variable stored therein until at least after it receives the completion message.
9. The method as defined by claim 1 wherein the multi-node shared-memory computer system comprises a given number of nodes, the set of accessing nodes having fewer nodes than the given number of nodes.
10. An apparatus for controlling access by a set of accessing nodes to shared memory of a home node, the home node and accessing nodes being part of a multi-node shared-memory computer system, the apparatus comprising:
control logic operatively coupled with the shared memory of the home node, the control logic determining if each node in the set of nodes has accessed the shared memory;
a message generator for generating a completion message having data indicating that each node in the set of nodes has accessed the shared memory of the home node; and
an interface operatively coupled with the message generator, the interface forwarding the completion message to each node in the set of nodes after it is determined that each node has accessed the shared memory.
11. The apparatus as defined by claim 10 wherein the control logic comprises:
an initializing module for setting a synchronization variable to an initial value;
a variable processor for updating the synchronization variable each time one of the set of nodes accesses the shared memory of the home node; and
a comparator for comparing the synchronization variable to a test variable according to a prescribed mathematical relationship after updating the synchronization variable.
12. The apparatus as defined by claim 11 wherein the interface determines that the synchronization variable matches satisfies the prescribed mathematical relationship with the test variable before forwarding the completion message.
13. The apparatus as defined by claim 12 wherein the synchronization variable matches satisfies the prescribed mathematical relationship with the test variable when both variables have equal values.
14. The apparatus as defined by claim 10 wherein the interface broadcasts the completion message to each accessing node in the set.
15. The apparatus as defined by claim 10 wherein each accessing node in the set of nodes is synchronized to execute a set of steps of a common process, each accessing node not executing a subsequent step in the common process until receipt of the completion message.
16. The apparatus as defined by claim 10 wherein the control logic detects when each node in the set of accessing nodes is to access the shared memory of the home node.
17. The apparatus as defined by claim 10 wherein the multi-node shared-memory computer system comprises a given number of nodes, the set of accessing nodes having fewer nodes than the given number of nodes.
18. A computer program product for use on a computer system for controlling access by a set of accessing nodes to shared memory of a home node, the home node and accessing nodes being part of a multi-node shared-memory computer system, the computer program product comprising a computer usable device having computer readable program code thereon, the computer readable program code comprising:
program code for determining that each node in the set of nodes has accessed the shared memory; and
program code for forwarding a completion message to each node in the set of nodes after it is determined that each node has accessed the shared memory, the completion message having data indicating that each node in the set of nodes has accessed the shared memory of the home node.
19. The computer program product as defined by claim 18 wherein determining comprises:
program code for setting a synchronization variable to an initial value;
program code for updating the synchronization variable each time one of the set of nodes accesses the shared memory of the home node; and
program code for comparing the synchronization variable to a test variable according to a prescribed mathematical relationship after updating the synchronization variable.
20. The computer program product as defined by claim 19 further comprising:
program code for determining that the synchronization variable matches satisfies the prescribed mathematical relationship with the test variable before forwarding the completion message.
21. The computer program product as defined by claim 20 wherein the synchronization variable matches satisfies the prescribed mathematical relationship with the test variable when both variables have equal values.
22. The computer program product as defined by claim 18 wherein the program code for forwarding comprises program code for broadcasting the completion message to each accessing node in the set.
23. The computer program product as defined by claim 18 wherein each accessing node in the set of nodes is synchronized to execute a set of steps of a common process, each accessing node not executing a subsequent step in the common process until receipt of the completion message.
24. The computer program product as defined by claim 18 further comprising:
program code for detecting that each node in the set of accessing nodes is to access the shared memory of the home node.
25. The computer program product as defined by claim 18 wherein a given node in the set of nodes includes a plurality of microprocessors, no more than one of the plurality of microprocessors accessing the shared memory.
26. The computer program product as defined by claim 18 further comprising program code for distributing a spinlock to the set of accessing nodes, the spinlock controlling access by the set of accessing nodes.
27. The computer program product as defined by claim 18 wherein the multi-node shared-memory computer system comprises a given number of nodes, the set of accessing nodes having fewer nodes than the given number of nodes.