IP Library › Assignment 040459/0157
Patent Assignment
Reel/Frame 040459/0157

Change of Name

Recorded: 2016-10-21 Pages: 5
Assignor
Assignee
SGI INTERNATIONAL, INC.
900 NORTH MCCARTHY BLVD, MILPITAS, CALIFORNIA, 95035
Covered Properties (70)
System for Multiprocessor Communication
Patent: 5,526,487 →
Application: 07/308,401 →
Cluster Architecture for a Highly Parallel Scalar/Vector Mulriprocessor System
Patent: 5,197,130 →
Application: 07/459,083 →
Method and Apparatus for Non-Sequential Resource Access
Patent: 5,208,914 →
Application: 07/535,786 →
Distributed Architecture for Input/Output for a Multiprocessor System
Patent: 5,168,547 →
Application: 07/536,182 →
Dedicated Centralized Signaling Mechanism for Selectively Signaling Devices in a Multiprocessor System
Patent: 5,239,629 →
Application: 07/536,192 →
Method and Apparatus for a Special Purpose Arithmetic Boolean Unit
Patent: 5,175,862 →
Application: 07/536,197 →
Global Registers for a Multiprocessor System
Patent: 5,165,038 →
Application: 07/536,198 →
Method and Apparatus for a Load and Flag Instruction
Application: 07/536,217 →
Method and Apparatus for a Multiple Request Toggling Priority System
Patent: 5,168,570 →
Application: 07/536,417 →
System and Method for Controlling a Highly Parallel Multiprocessor Using an Anarchy Based Scheduler for Parallel Execution Thread Scheduling
Patent: 5,179,702 →
Application: 07/537,466 →
Vector Bit and Word Shift Functional Unit for Supercomputer Processor
Application: 07/618,748 →
Method and Apparatus for Separate Memory Hazard Mark and Wait Instructions for Processors Having Multiple Memory Ports
Application: 07/911,649 →
Method and Apparatus for a Unified Parallel Processing Architecture
Patent: 5,428,803 →
Application: 07/912,964 →
Method and Apparatus for Load and Flag Instruction
Application: 07/920,155 →
Method for Clocking Functional Units in One Cycle by Using a Single Clock for Routing Clock Inputs to Initiate Receive Operations Prior to Transmit Operations
Patent: 5,495,596 →
Application: 07/923,086 →
Global Registers for a Multiprocessor System
Application: 07/976,899 →
Retaining and Release Mechanism for Computer Storage Devices Including a Pawl Latch Assembly
Patent: 5,269,698 →
Application: 08/009,576 →
Optical Clock Distribution System
Patent: 5,537,498 →
Application: 08/027,049 →
High Memory Capacity Dram Simm
Patent: 5,272,664 →
Application: 08/049,803 →
A System and Method of Implementing Read Resources to Maintain Cache Coherency in a Multiprocessor Environment Permitting Split Transactions
Patent: 5,504,874 →
Application: 08/128,080 →
A System and Method for Fair Arbitration on a Multi-Domain Multiprocessor Bus
Patent: 5,509,125 →
Application: 08/128,082 →
System and Method for Generating a Read-Modify-Write Operation
Patent: 5,544,331 →
Application: 08/128,720 →
Method and Apparatus for Locking Shared Memory Locations in Multiprocessing Systems
Patent: 5,535,365 →
Application: 08/141,259 →
Method and Apparatus for Separate Mark and Wait Instructions for Processors Having Multiple Memory Ports
Application: 08/165,012 →
Barrier Synchronization for Distributed Memory Massively Parallel Processing Systems
Patent: 5,434,995 →
Application: 08/165,265 →
System for Allocating Messages Between Virtual Channels to Avoid Deadlock and to Optimize the Amount of Message Traffic on Each Type of Virtual Channel
Patent: 5,583,990 →
Application: 08/165,266 →
Method for the Dynamic Allocation of Array Sizes in a Multiprocessor System
Patent: 5,586,325 →
Application: 08/165,379 →
Repetitive Signal Detector for Preventing Thermal Runaway
Patent: 5,418,481 →
Application: 08/165,747 →
Method of Managing Distributed Memory Within a Massively Parallel Processing System
Patent: 5,566,321 →
Application: 08/166,293 →
Messaging Facility with Hardware Tail Pointer and Software Implemented Head Pointer Message Queue for Distributed Memory Massively Parallel Processing System
Patent: 5,581,705 →
Application: 08/166,443 →
Vector Shift Functional Unit for Successively Shifting Operands Stored in a Vector Register by Corresponding Shift Counts Stored in Another Vector Register
Patent: 5,481,746 →
Application: 08/218,997 →
Fiber Optic Channel Extender Interface Method and Apparatus
Patent: 5,420,583 →
Application: 08/250,375 →
Interleaved Memory Access System Having Variable-Sized Segments Logical Address Spaces and Means for Dividing/Mapping Physical Address into Higher and Lower Order Addresses
Patent: 5,561,784 →
Application: 08/268,660 →
Extendible Clock Mechanism
Patent: 5,625,831 →
Application: 08/331,730 →
Method and Apparatus for Accessing Global Registers in a Multiprocessor System
Patent: 5,524,255 →
Application: 08/379,123 →
Communication Protocol for Transferring Information Across a #S Serial Communication Link
Patent: 5,592,487 →
Application: 08/407,808 →
System for Continuously Recirculating Negatively Acknowledged Requests of the Source Until the Negatively Acknowledged Requests Are Accepted by Flow Control Associated with Each Target
Application: 08/435,448 →
Apparatus and Method for Page Migration in a Non-Uniform Memory Access (Numa) System
Application: 08/435,464 →
High Memory Capacity Dimm with Data and State Memory
Application: 08/440,214 →
Dimm Pair with Data Memory and State Memory
Application: 08/440,967 →
Vector Word Shift by Vo Shift Count in Vector Supercomputer Processor
Patent: 5,848,286 →
Application: 08/521,566 →
A System and Method of Implementing Read Resources to Maintain Cache Coherency in a Multiprocessor Environment Permitting Split Transactions
Patent: 5,664,151 →
Application: 08/578,997 →
Cooling Cap Method and Apparatus for Tab Packaged Integrated Circuits
Patent: 5,805,418 →
Application: 08/604,918 →
Networked Multiprocessor System with Global Distributed Memory and Block Transfer Engine
Patent: 5,797,035 →
Application: 08/661,908 →
Multiprocessor Computer System with Interleaved Processing Element Nodes
Patent: 5,737,628 →
Application: 08/662,868 →
Array Address and Loop Alignment Calculations
Application: 08/675,771 →
Recursive Address Centrifuge for Distributed Memory Massively Parallel Processing Systems
Patent: 6,119,198 →
Application: 08/889,251 →
Vector Shift Functional Unit for Successively Shifting Operands Stored in a Vector Register by Corresponding Shift Counts Stored in Another Vector Register
Patent: 6,098,162 →
Application: 09/138,613 →
Printed Circuit Board Stiffener
Patent: 6,512,676 →
Application: 09/619,725 →
Memory daughter card apparatus, configurations, and methods
Application: 09/620,178 →
Backshell assembly
Application: 09/730,077 →
Publication: US 2002/0001989
System, method, and computer program product for capturing a visualization session
Application: 09/995,668 →
Publication: US 2002/0063715
Extended attribute caching in clustered filesystem
Application: 10/197,211 →
Publication: US 2003/0028514
Method for Performing Cache Coherency in a Computer System
Patent: 7,802,058 →
Application: 10/837,057 →
Node Synchronization for Multi-Processor Computer Systems
Patent: 7,464,115 →
Application: 11/113,805 →
Publication: US 2006/0242308
Liquid DIMM Cooler
Application: 11/121,975 →
Publication: US 2006/0250772
Network topology for a scalable multiprocessor system
Application: 11/295,676 →
Publication: US 2006/0282648
Sub rack based vertical housing for computer systems
Application: 11/386,382 →
Publication: US 2006/0158841
Hot Plug Control Apparatus and Method
Patent: 7,868,656 →
Application: 12/463,941 →
Publication: US 2009/0276555
Method for Empirically Determining a Qualified Bandwidth of File Storage for a Shared Filed System Using a Guaranteed Rate I/O (Grio) or Non-Grio Process
Patent: 7,908,410 →
Application: 12/538,020 →
Publication: US 2010/0017545
Method for Performing Cache Coherency in a Computer System
Patent: 8,402,225 →
Application: 12/887,374 →
Publication: US 2011/0016277
Method for Performing Cache Coherency in a Computer System
Application: 13/846,731 →
Publication: US 2013/0282988
Network Topology for a Scalable Multiprocessor System
Patent: 9,514,092 →
Application: 13/873,058 →
Publication: US 2013/0246653
Housing for Deskside Computer
Patent: 393,249 →
Application: 29/060,131 →
Compact Computer Housing
Patent: 395,286 →
Application: 29/060,203 →
Compact Computer Housing
Patent: 396,698 →
Application: 29/065,316 →
Computer Housing
Patent: 417,203 →
Application: 29/096,304 →
Backshell assembly
Application: 60/215,472 →
System and method for reducing back flow
Application: 60/648,668 →
Directory delegation and update pushing in shared memory microprocessor systems
Application: 60/676,551 →
Related Assignments (16)
Other recorded transfers of the patents in this record — the chain of ownership.
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests... Apr 24, 2014
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0001 →
Merger Apr 24, 2014
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 032758/0516 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests... Apr 24, 2014
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0847 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests... Apr 24, 2014
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS, INC.
Reel/Frame 032757/0467 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests. Jul 26, 2016
From: FOOTHILL CAPITAL CORPORATION
To: SILICON GRAPHICS, INC.
Reel/Frame 039474/0606 →
Merger Jul 26, 2016
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 039474/0796 →
Order...Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Encumbrances, and Interests. Jul 26, 2016
From: MORGAN STANLEY & CO., INCORPORATED
To: SILICON GRAPHICS, INC.
Reel/Frame 039482/0015 →
Order. . .Authorizing the Sale of All or Substantially All of the Assets of the Debtors Free and Clear of All Liens, Claims, Encumbrances, and Interests Jul 27, 2016
From: U.S. BANK NATIONAL ASSOCIATION, AS TRUSTEE
To: SILICON GRAPHICS, INC
Reel/Frame 039484/0869 →
Assignment of Assignor's Interest Oct 21, 2016
From: CRAY RESEARCH, L.L.C.
To: SILICON GRAPHICS, INC.
Reel/Frame 040092/0651 →
Merger Oct 21, 2016
From: CRAY RESEARCH, INC.
To: CRAY RESEARCH, L.L.C.
Reel/Frame 040464/0893 →
Assignment of Assignor's Interest Oct 21, 2016
From: SILICON GRAPHICS, INC
To: SILICON GRAPHICS INTERNATIONAL, INC.
Reel/Frame 040459/0026 →
Merger Oct 21, 2016
From: SGI INTERNATIONAL, INC.
To: SILICON GRAPHICS INTERNATIONAL CORP.
Reel/Frame 040459/0518 →
Assignment of Assignor's Interest Oct 24, 2016
From: BEARD, DOUGLAS R; HESSEL, RICHARD E; MILLER, EDWARD C; PHELPS, ANDREW E
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 040105/0284 →
Assignment of Assignor's Interest Oct 24, 2016
From: ECKERT, ROGER E; HESSEL, RICHARD E; PHELPS, ANDREW E; SPIX, GEORGE A
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 040105/0049 →
Assignment of Assignor's Interest Oct 24, 2016
From: ECKERT, ROGER E; HESSEL, RICHARD E; PHELPS, ANDREW E; SPIX, GEORGE A
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 040105/0146 →
Assignment of Assignor's Interest Oct 4, 2017
From: SILICON GRAPHICS INTERNATIONAL CORP.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 044128/0149 →