Granted Patent B1

US 7,802,058 · App. 10/837,057 · Granted Sep 21, 2010

Abstract

Claims (34)

1. A method for performing cache coherency in a computer system, comprising:

selecting a first one of a plurality of coherency protocols for a first memory transaction;

performing cache coherency for the first memory transaction on caches in the computer system by applying a first set of cache states to cached data in accordance with the first one of the plurality of coherency protocols selected for the first memory transaction;

selecting a second one of a plurality of coherency protocols for a second memory transaction, the second one of the plurality of coherency protocols selected for the second memory transaction being different than the first one of the plurality of coherency protocols selected for the first memory transaction;

performing cache coherency for the second memory transaction on caches in the computer system by applying a second set of cache states to cached data in accordance with the second one of the plurality of coherency protocols selected for the second memory transaction;

wherein selection among the plurality of cache coherency protocols is performed on a dynamic basis for each separate memory transaction to be processed.

2. The method of claim 1 , wherein the selected one of the plurality of coherency protocols is a write invalidate protocol.

3. The method of claim 2 , wherein the write invalidate protocol generates invalidate messages in response to a change in data pursuant to the first memory transaction for caches in the computer system holding a copy of the data.

4. The method of claim 1 , wherein the selected one of the plurality of coherency protocols is an update protocol.

5. The method of claim 4 , wherein the update protocol does not make data associated with the first memory transaction exclusive before executing memory location stores.

6. The method of claim 5 , wherein new data to be stored is transmitted to all caches in a computing system that hold copies of the original data.

7. The method of claim 1 , wherein the selected one of the plurality of coherency protocols is an exclusive protocol.

8. The method of claim 7 , wherein data associated with the first memory transaction is requested to be placed into an exclusive state in response to the data not being stored on a local cache associated with the origination of the first memory transaction.

9. The method of claim 1 , wherein the selected one of the plurality of coherency protocols is an update once protocol.

10. A computer readable medium tangibly storing code for performing cache coherency in a computer system, the code operable to:

select a first one of a plurality of coherency protocols for a first memory transaction;

perform cache coherency for the first memory transaction on caches in the computer system by applying a first set of cache states to cached data in accordance with the first one of the plurality of coherency protocols selected for the first memory transaction;

select a second one of a plurality of coherency protocols for a second memory transaction, the second one of the plurality of coherency protocols selected for the second memory transaction being different than the first one of the plurality of coherency protocols selected for the first memory transaction;

perform cache coherency for the second memory transaction on caches in the computer system by applying a second set of cache states to cached data in accordance with the second one of the plurality of coherency protocols selected for the second memory transaction;

wherein selection among the plurality of cache coherency protocols is performed on a dynamic basis for each separate memory transaction to be processed.

11. The computer readable medium of claim 10 , wherein the plurality of coherency protocols includes an invalidate protocol, an update protocol, an exclusive protocol, and an update once protocol.

12. The computer readable medium of claim 10 , wherein the code is further operable to:

update a directory associated with each cache pursuant to the selected one of the plurality of coherency protocols.

13. The computer readable medium of claim 10 , wherein each of the plurality of coherency protocols is associated with particular data.

14. A system for performing cache coherency in a computer system, comprising:

means for selecting a first one of a plurality of coherency protocols for a first memory transaction;

means for performing cache coherency for the first memory transaction on caches in the computer system by applying a first set of cache states to cached data in accordance with the first one of the plurality of coherency protocols selected for the first memory transaction;

means for selecting a second one of a plurality of coherency protocols for a second memory transaction, the second one of the plurality of coherency protocols selected for the second memory transaction being different than the first one of the plurality of coherency protocols selected for the first memory transaction;

means for performing cache coherency for the second memory transaction on caches in the computer system by applying a second set of cache states to cached data in accordance with the second one of the plurality of coherency protocols selected for the second memory transaction;

wherein selection among the plurality of cache coherency protocols is performed on a dynamic basis for each memory transaction type to be processed.

15. The system of claim 14 , wherein the plurality of coherency protocols includes an invalidate protocol, an update protocol, an exclusive protocol, and an update once protocol.

16. The system of claim 14 , further comprising:

updating a directory associated with each cache pursuant to the selected one of the plurality of coherency protocols.

17. The system of claim 14 , wherein each of the plurality of coherency protocols is associated with particular data.

Assignments (13)