System and method for removing data from processor caches in a distributed multi-processor computer system
View Patent ↗A processor ( 600 ) in a distributed shared memory multi-processor computer system ( 10 ) may initiate a flush request to remove data from its cache. A processor interface ( 24 ) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors ( 601 ) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface ( 24 ) initiates removal of the data from the cache of the identified processor ( 601 ). The identified processor ( 601 ) initiates a writeback to a memory directory interface unit ( 24 ) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface ( 24 ) forwards the flush request to the memory directory interface unit ( 22 ). Memory directory interface unit ( 22 ) determines which remote processors within the system ( 10 ) have a copy of the data and forwards the flush request only to those identified processors. The identified processors then remove the data from their respective caches in response to the flush request. If an identified remote processor has modified data, the identified remote processor initiates a writeback to the memory directory interface unit ( 22 ) for preservation of the modified data.
1. A method for maintaining the state of a of cache line, the method comprising:
receiving a request message at a memory directory unit relating to the cache line from a requestor;
determining whether a first processor maintains a copy of the cache line when the received request message is a flush of the cache line;
forwarding a flush request of the cache line to the first processor when the received request message is a flush of the cache line;
receiving a modified copy of the cache line by the memory directory unit when the first processor has a modified copy of the cache line, and when the received request is a flush of the cache line;
determining whether the priority of the received message is greater than or equal to the priority of a directory entry in the memory directory unit;
forwarding a message in response to receiving the request message when the priority of the received message is greater than or equal to the priority of the directory entry;
receiving a response to the forwarded message;
responding to the request message with a negative acknowledgement (NACK) when the priority of the request message is less than the priority of the directory entry; and
not modifying the priority of the directory entry when the priority of the request message is less than the priority of the directory entry.
2. The method of claim 1 , further comprising updating the modified cache line in memory by the memory directory unit.
3. The method of claim 1 , further comprising;
determining whether the requestor of the requested message has read permission to the cache line when the requested message is a read request;
responding to the requested message with an error when it is determined that the requestor does not have read permission to the cache line; and
sending the requested data when it is determined that the requestor has read permission to the cache line.
4. The method of claim 1 , further comprising;
determining whether the requestor of the requested message has write permission to the cache line when the requested message is a write request;
responding to the requested message with an error when it is determined that the requestor does not have write permission to the cache line writing the cache line to memory when it is determined that the requestor has write permission to the cache line.
5. The method of claim 1 , further comprising re-setting the priority of the directory entry to zero when the forwarded message is serviced successfully.
6. The method of claim 1 , further comprising setting the priority of the directory entry to the priority of the request message when the forwarded message is not serviced successfully.
7. The method of claim 1 , further comprising:
determining whether the requestor of the requested message has read permission to the cache line when the requested message is a read request;
responding to the requested message with an error when it is determined that the requestor does not have read permission to the cache line; and
sending the requested data when it is determined that the requestor has read permission to the cache line.
8. The method of claim 1 , further comprising:
determining whether the requestor of the requested message has write permission to the cache line when the requested message is a write request;
responding to the requested message with an error when it is determined that the requestor does not have write permission to the cache line
writing the cache line to memory when it is determined that the requestor has write permission to the cache line.
9. The method of claim 1 , further comprising incrementing a negative acknowledgement count, wherein the negative acknowledgement count corresponds to the number of time the request message has been NACK'd.
10. The method of claim 9 , further comprising:
detecting that the requested message has been excessively NACK'd; and
sending an intervention request, an invalidate request, or a backoff response.
11. The method of claim 1 , further comprising:
receiving a read request to the modified copy of the cache line by the memory directory unit from a second processor prior to receiving the modified copy of the cache line from the first processor by the memory directory unit;
generating an intervention message by the memory directory unit; and
sending a response to the second processor by the memory directory unit, wherein the response includes the cache line requested by the second processor.
12. The method of claim 11 , further comprising:
updating the cache line by the memory directory unit when the modified cache line from the first processor is received prior to receiving the cache line modified by the second processor; and
updating the cache line by the memory directory unit when the modified cache line from the second processor is received.
13. The method of claim 11 , further comprising:
receiving a relinquish message from the second processor by the memory directory unit when the second processor has dropped the cache line.
14. The method of claim 11 , further comprising receiving the cache line by the memory directory unit when the cache line is modified by the second processor.
15. The method of claim 14 , further comprising:
updating the cache line by the memory directory unit when the modified cache line from the second processor is received.