EXTERNAL ACCESS OF INTERNAL SAS TOPOLOGY IN STORAGE SERVER
The SAS expander PCBA is partitioned to allow SAS lanes to be externalized, allowing for a x4 wide port external access into each of the two primary SAS expander modules and each of the two secondary SAS expander modules. This configuration allows for a single host x8 external HBA connection to tunnel into the storage array by connecting into either the primary or secondary x4 wide ports. A second host may connect to the alternate connection if desired. This configuration may also lend itself to allow up to four hosts to access the internal SAS topology of the Enclosure. This configuration may also lend itself to connecting the primary and secondary SAS expander modules together in applications that require an SAS expander to see more storage device arrays than would normally be confined to a typical SAS expander module.
1 . An SAS expander circuit, comprising:
a printed circuit board assembly (PCBA) including a plurality of SAS lanes, the SAS lanes providing external access to at least one primary module and at least one secondary module;
circuitry for connecting the primary module and the secondary module to an array of storage devices within a storage server.
2 . The circuit of claim 1 , wherein the PCBA is communicatively coupled to a Midplane PCBA.
3 . The circuit of claim 1 , wherein the PCBA is not communicatively coupled to a host bus adaptor.
4 . The circuit of claim 1 , wherein the external access is through an SAS cable connection.
5 . The circuit of claim 1 , wherein the circuit includes two primary modules and two secondary modules.
6 . The circuit of claim 1 , wherein the circuit can be coupled to a storage server circuitry during operation of the server without affecting I/O operations of the server.
7 . The circuit of claim 1 , further comprising a plurality of LEDS, wherein the state of the LEDs indicates fault information for the circuit.
8 . The circuit of claim 1 , further comprising an enclosure processor interface which allows remote debugging of the circuit.
9 . The circuit of claim 1 , wherein the circuit can be coupled to one or more fan connectors.