Granted Patent B1

US 6,856,950 · App. 09/418,706 · Granted Feb 15, 2005

Abstract

Claims (109)

1. A logic verification system, comprising:

a hardware simulator;

a diagnostic system capable of running a diagnostic program;

an interprocess communication mechanism for transferring stimulus from the diagnostic system to the hardware simulator and for transferring results from the hardware simulator to the diagnostic system; and

a verification environment, wherein the verification environment includes two or more layers of abstraction placed between logic being verified and the diagnostic program, wherein the layers of abstraction include:

a logic design representative of the logic being verified;

a logic design wrapper; and

a verification kernel, wherein the verification kernel includes a diagnostic kernel and a simulation kernel, wherein the diagnostic kernel and the simulation kernel communicate through the interprocess communication mechanism;

wherein the logic design, the logic design wrapper and the simulation kernel are linked to form a logic simulator.

2. The logic verification system according to claim 1 , wherein the verification environment further includes a diagnostic programming interface, and wherein the diagnostic program, the diagnostic programming interface and the diagnostic kernel are linked to form a diagnostic test.

3. The logic verification system according to claim 2 , wherein the diagnostic programming interface is a program library that adapts abstract data structures in the diagnostic program to structures in the verification kernel.

4. The logic verification system according to claim 2 , wherein the diagnostic kernel is a program library which operates on events.

5. The logic verification system according to claim 4 , wherein events include wiggles and bundles.

6. The logic verification system according to claim 4 , wherein the verification environment further includes a logic design representative of the device being verified and a logic design wrapper, and wherein the logic design, the logic design wrapper and the simulation kernel are linked to form a logic simulator.

7. The logic verification system according to claim 6 , wherein the logic design wrapper is a program library that adapts the simulation kernel to the logic design.

8. The logic verification system according to claim 4 , wherein the verification environment further includes a four-state variable data structure.

9. The logic verification system according to claim 1 , wherein the logic design wrapper includes a program library that adapts the simulation kernel to the logic design.

10. The logic verification system according to claim 1 , wherein the simulation kernel includes a program library which operates on events.

11. The logic verification system according to claim 1 , wherein the simulation kernel includes a program library which operates on wiggles and bundles.

12. The logic verification system according to claim 1 , wherein the simulation kernel is a program library which operates on events.

13. The logic verification system according to claim 1 , wherein the simulation kernel is a program library which operates on wiggles and bundles.

14. The logic verification system according to claim 1 , wherein the verification environment further includes a group data structure used to declare an array of undetermined length.

15. The logic verification system according to claim 14 , wherein the verification environment further includes a length function, wherein the length function returns length of an array declared using the group data structure.

16. A logic verification system, comprising:

a hardware simulator;

a diagnostic system;

an interprocess communication mechanism for transferring stimulus from the diagnostic system to the hardware simulator and for transferring results from the hardware simulator to the diagnostic system;

a verification environment, wherein the verification environment includes two or more layers of abstraction placed between logic being verified and a diagnostic program, wherein one of the layers of abstraction is a verification kernel, wherein the verification kernel includes a diagnostic kernel and a simulation kernel and wherein the diagnostic kernel and the simulation kernel communicate through the interprocess communication mechanism; and

wherein the verification environment further includes a plurality of ports, including an event port, wherein the event port drives and captures events.

17. The logic verification system according to claim 16 , wherein the plurality of ports includes a memory back door port, wherein the memory back door port is used to construct a memory model.

18. A logic verification system, comprising:

a hardware simulator;

a diagnostic system;

an interprocess communication mechanism for transferring stimulus from the diagnostic system to the hardware simulator and for transferring results from the hardware simulator to the diagnostic system;

a verification environment, wherein the verification environment includes two or more layers of abstraction placed between logic being verified and a diagnostic program, wherein one of the layers of abstraction is a verification kernel, wherein the verification kernel includes a diagnostic kernel and a simulation kernel and wherein the diagnostic kernel and the simulation kernel communicate through the interprocess communication mechanism; and

wherein the verification environment diagnostic program generates stimulus via a DPI apply.

19. A method of verifying an electronic system, comprising:

providing a verification kernel;

expressing the electronic system as a logic design;

defining a wrapper, wherein the wrapper is an interface between the logic design and the verification kernel;

placing tests to be run against the logic design within a diagnostic program;

defining a diagnostic program interface, where the diagnostic program interface is an interface between the diagnostic program and the verification kernel;

executing the tests against the logic design;

reporting results of the tests; and

validating the results against expected results;

wherein defining a wrapper includes compiling the logic design and the wrapper into an object file, wherein the object file is linked with verification kernel routines to create an executable logic simulator.

20. The method according to claim 19 , wherein executing the tests against the logic design includes establishing an inter-process communication (IPC) layer between the diagnostic program and the logic simulator.

21. A method of verifying an electronic system, comprising:

providing a verification kernel;

expressing the electronic system as a logic design;

defining a wrapper, wherein the wrapper is an interface between the logic design and the verification kernel;

placing tests to be run against the logic design within a diagnostic program;

defining a diagnostic program interface, where the diagnostic program interface is an interface between the diagnostic program and the verification kernel;

executing the tests against the logic design;

reporting results of the tests; and

validating the results against expected results;

wherein executing includes executing recovery code when an exception is detected.

22. The method according to claim 21 , wherein executing further includes trapping to a handler routine on occurrence of an exception.

23. The method according to claim 21 , wherein executing further includes cooperative multitasking of a plurality of threads.

24. The method according to claim 23 , wherein cooperative multitasking includes communicating between threads via a semaphore variable.

25. The method according to claim 23 , wherein cooperative multitasking includes controlling execution of threads via a barrier function.

26. The method according to claim 21 , wherein executing further includes waiting for a nondeterministic outcome.

27. The method according to claim 21 , wherein executing further includes popping events off an event queue.

28. A method of verifying an electronic system, comprising:

providing a verification kernel;

expressing the electronic system as a logic design;

defining a wrapper, wherein the wrapper is an interface between the logic design and the verification kernel;

placing tests to be run against the logic design within a diagnostic program;

defining a diagnostic program interface, where the diagnostic program interface is an interface between the diagnostic program and the verification kernel;

executing the tests against the logic design;

reporting results of the test; and

validating the results against expected results;

wherein executing includes popping wiggles off a wiggle queue and popping bundles off one or more bundles queues.

29. The method according to claim 28 wherein executing includes performing an examine function to detect a change of state.

30. A method of verifying an electronic system, comprising:

providing a verification kernel;

expressing the electronic system as a logic design;

defining a wrapper, wherein the wrapper is an interface between the logic design and the verification kernel;

placing tests to be run against the logic design within a diagnostic program;

defining a diagnostic program interface, where the diagnostic program interface is an interface between the diagnostic program and the verification kernel;

executing the tests against the logic design;

reporting results of the tests; and

validating the results against expected results;

wherein executing includes referencing memories built using memory access PLI tasks.

31. A system for simulating operation of an electronic device, comprising:

a hardware simulator;

a diagnostic system; and

an interprocess communication mechanism for transferring stimulus from the diagnostic system to the hardware simulator and for transferring results from the hardware simulator to the diagnostic system;

wherein the simulator is capable of receiving connections and commands from a diagnostic program running on the diagnostic system, of executing the commands as directed and of returning results to the diagnostic system; and

wherein the hardware simulator includes a simulator kernel, a logic design wrapper and a logic design representative of the electronic device.

32. The system according to claim 31 , wherein the logic design wrapper includes a program library that adapts the simulation kernel to the logic design.

33. The system according to claim 32 , wherein the simulation kernel includes a program library which operates on events.

34. The system according to claim 32 , wherein the simulation kernel includes a program library which operates on wiggles and bundles.

35. The system according to claim 31 , wherein the diagnostic system includes a group data structure used to declare an array of undetermined length.

36. The system according to claim 35 , wherein the diagnostic system includes a length function, wherein the length function returns length of an array declared using the group data structure.

37. The system according to claim 31 , wherein the diagnostic system includes a four-state variable data structure.

38. A system for simulating operation of an electronic device, comprising:

a hardware simulator;

a diagnostic system; and

an interprocess communication mechanism for transferring stimulus from the diagnostic system to the hardware simulator and for transferring results from the hardware simulator to the diagnostic system;

wherein the simulator is capable of receiving connections and commands from a diagnostic program running on the diagnostic system, of executing the commands as directed and of returning results to the diagnostic system; and

wherein the diagnostic system includes a plurality of ports, including an event port, wherein the event port drives and captures events.

39. The system according to claim 38 , wherein the plurality of ports includes a memory back door port, wherein the memory back door port is used to construct a memory model.

40. A system for simulating operation of an electronic device, comprising:

a hardware simulator;

a diagnostic system; and

an interprocess communication mechanism for transferring stimulus from the diagnostic system to the hardware simulator and for transferring results from the hardware simulator to the diagnostic system;

wherein the simulator is capable of receiving connections and commands from a diagnostic program running on the diagnostic system, of executing the commands as directed and of returning results to the diagnostic system; and

wherein the diagnostic program generates stimulus via a DPI apply.

Assignments (8)