System and method for adaptively deskewing parallel data signals relative to a clock
View Patent ↗A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.
1. A method of reducing skew between a plurality of signals transmitted with a transmit clock, wherein the plurality of signals includes a first signal and a second signal, the method comprising:
receiving the transmit clock and each of the plurality of signals;
detecting skew between the received transmit clock and each of the received signals;
passing each of the plurality of received signals through a separate delay line, wherein passing each of the plurality of received signals through a separate delay line includes adding delay to one or more of the plurality of received signals to compensate for the detected skew;
phase comparing each of the plurality of delayed signals to a reference signal to detect changes in the detected skew; and
modifying the delay added to each of the plurality of delayed signals to adapt to changes in the detected skew.
2. The method of claim 1 , wherein phase comparing includes generating a clock early signal and a data early signal for each of the plurality of signals.
3. The method of claim 1 , wherein each delay line includes a plurality of taps and wherein setting delay includes selecting one of the plurality of taps.
4. The method of claim 3 , wherein each delay line includes a plurality of feedback positions and wherein setting delay includes selecting one of the plurality of feedback positions.
5. The method of claim 1 , wherein detecting skew includes:
doubling the received transmit clock to form a doubled clock; and
clocking a phase comparator circuit with the doubled clock.
6. The method of claim 5 , wherein the phase comparator circuit generates a clock early signal and a data early signal for each of the plurality of received signals and wherein adding delay includes:
passing each of the plurality of received signals through a separate delay line; and
setting delay as a function of the clock early and data early signals, wherein setting delay includes determining a minimum latency through the delay lines.
7. The method of claim 6 , wherein each delay line includes a plurality of taps and wherein setting delay includes selecting one of the plurality of taps.
8. The method of claim 6 , wherein each delay line includes a plurality of feedback positions and wherein setting delay includes selecting one of the plurality of feedback positions.
9. The method of claim 1 , wherein adding delay includes capturing each of the plurality of received signals in an output register.