High speed software driven emulator comprised of a plurality of emulation processors with a method to allow high speed bulk read/write operation synchronous DRAM while refreshing the memory
View Patent ↗A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.
1. In a software driven emulator comprised of a plurality of printed circuit boards each having a module, each of said modules including a processor chip and at least one SDRAM coupled to the processor chip, a maintenance bus coupled to said SDRAM, and a memory controller coupled to said maintenance bus, a method of executing bulk data transfers to said SDRAM via said maintenance bus, comprising:
setting a latch in said memory controller to halt data transfer between said SDRAM and said processor chip, said processor chip including a plurality of emulation processors;
transferring data in bursts to said SDRAM from the plurality of emulation processors via said maintenance bus on each clock cycle for a predetermined number of clock cycles in succession;
halting the transfer of data after said predetermined number of clock cycles;
initiating a SDRAM refresh cycle after said halting;
resuming said transferring data in bursts upon receipt of a done signal after said refresh cycle.
2. In a software driven emulator comprised of a plurality of printed circuit boards each having a module, each of said modules including a processor chip and at least one SDRAM coupled to the processor chip, a maintenance bus coupled to said SDRAM, and a memory controller coupled to said maintenance bus, a method of executing bulk data transfers from said SDRAM via said maintenance bus, comprising:
setting a latch in said memory controller to halt data transfer between said SDRAM and said processor chip, said processor chip including a plurality of emulation processors;
transferring data in bursts from said SDRAM to the plurality of emulation processors via said maintenance bus on each clock cycle for a predetermined number of clock cycles in succession;
halting the transfer of data after said predetermined number of clock cycles;
initiating a SDRAM refresh cycle after said halting;
resuming said transferring data in bursts upon receipt of a done signal after said refresh cycle.
3. A method of executing bulk transfers as in claim 1 including establishing a starting address for said bulk transfer in said memory controller and incrementing said starting address by one on each clock cycle.
4. A method of executing bulk transfers as in claim 2 including establishing a starting address for said bulk transfer in said memory controller and incrementing said starting address by one on each clock cycle.
5. A method of executing bulk transfers as in claim 1 wherein a data word is transferred on each clock cycle.
6. A method of executing bulk transfers as in claim 2 wherein a data word is transferred on each clock cycle.