IP Library Granted Patent US 6,928,627
Granted Patent B1
US 6,928,627 · App. 09/675,343 · Granted Aug 9, 2005

Method for recognizing and avoiding etch-critical regions

Assignee: Siemens Aktiengesellschaft
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Quick Facts
Patent No.
US 6,928,627
App. No.
09/675,343
Granted
Aug 9, 2005
Kind
B1
Abstract

In a method for recognizing etch-critical regions, the critical regions are already determined in the layout under the processor control dependent on the fabrication-oriented rules and are automatically rectified in the existing layout, so that under-etchings are avoided in the following etching procedures.

Claims (13)

1. A method for recognizing and rectifying etch-critical regions, said method comprising:

determining the data structure of a layout;

determining the data structure of the configuration elements arranged in a plane of the layout;

determining the critical regions between the configuration elements;

modifying the critical regions; and

visually displaying the modified critical regions;

wherein the determining of the critical regions is at least partially based upon a height and a spacing of a coating to be etched off.

2. The method according to claim 1 , wherein the modifying of the critical regions is undertaken so that no under-etching occurs, and said modified critical regions are integrated into the existing data structure of the layout.

3. The method according to claim 1 , wherein the critical regions are adjustable by an admissible, fabrication-oriented, minimal spacing between the configuration elements.

4. The method according to claim 3 , wherein the critical regions between the configuration elements are filled out by polygons so that the critical regions between the configuration elements are avoided.

5. The method according to claim 4 , wherein the polygons of the critical regions are limited given possible superimpositions of the configuration elements.

6. The method according to claim 5 , wherein the polygons of the critical regions are enlarged slightly so that the edges of the polygons superimpose with the edges of the configuration elements.

7. The method according to claim 1 , further comprising scanning the data structure of the layout using an optical scanner.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2009
From: SIEMENS AKTIENGESELLSCHAFT
To: TRANSPACIFIC SILICA, LLC
Reel/Frame 022529/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2001
From: VOGL, THOMAS
To: SIEMENS AKTIENGESELLSCHAFT
Reel/Frame 011514/0330 →
Priority Claims (1)
DE 199 46 753 · Sep 29, 1999 · national