IP Library Granted Patent US 6,979,654
Granted Patent B2
US 6,979,654 · App. 09/681,986 · Granted Dec 27, 2005

Method of avoiding dielectric layer deterioation with a low dielectric constant during a stripping process

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,979,654
App. No.
09/681,986
Granted
Dec 27, 2005
Kind
B2
Abstract

A low k dielectric layer is formed on a surface of a substrate of a semiconductor wafer. Then, a surface treatment is performed to the low k dielectric layer to form a passivation layer on a surface of the low k dielectric layer. A patterned photoresist layer is formed over the surface of the semiconductor wafer. The patterned photoresist layer is then used as a hard mask to perform an etching process on the low k dielectric layer. Finally, a stripping process is performed to remove the patterned photoresist layer. The passivation layer is used to prevent deterioration of the dielectric characteristic of the low k dielectric layer during the stripping process.

Claims (26)

1. A method for avoiding deterioration of a dielectric characteristic of a dielectric layer having a low dielectric constant (low k) during a stripping process, the dielectric layer formed on a surface of a substrate, the method comprising:

performing surface treatment to the low k dielectric layer to form a passivation layer on a surface of the low k dielectric layer;

forming a patterned photoresist layer over the substrate;

using the photoresist layer as a hard mask to perform an etching process on the low k dielectric layer; and

performing a stripping process.

2. The method of claim 1 wherein the substrate is a silicon substrate provided by a silicon wafer.

3. The method of claim 1 wherein the low k dielectric layer is composed of HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), H-PSSQ (hydrio polysilsesquioxane), M-PSSQ (methyl polysilsesquioxane), P-PSSQ (phenyl polysilsesquioxane) or HOSP.

4. The method of claim 3 wherein the low k material is formed on the substrate by performing a chemical vapor deposition (CVD) process or a spin-on process.

5. The method of claim 1 wherein the surface treatment is a plasma treatment.

6. The method of claim 5 wherein the plasma treatment is performed in a nitrogen-containing environment to form the passivation layer on the surface of the low k dielectric layer.

7. The method of claim 6 wherein the nitrogen-containing environment comprises nitrous oxide (N 2 O), nitric oxide (NO), or ammonia (NH 3 ).

8. The method of claim 6 wherein the plasma treatment utilizes a radio frequency (RF) with a power of about 100 to 300 Watts (W), a process pressure between 10 −3 and 10 −6 Torr, a process time of less than 20 minutes, and a process temperature of the substrate that is less than 250° C.

9. The method of claim 1 wherein the stripping process is a wet stripping process, and the passivation layer is used to avoid formation of Si—OH bonds in the low k dielectric layer during the wet stripping process.

10. A method for avoiding deterioration of a dielectric characteristic of a low k dielectric layer, the low k dielectric layer formed on a substrate, the method comprising:

performing a surface treatment to the low k dielectric layer to form a passivation layer on a surface of the low k dielectric layer;

forming a patterned photoresist layer over the substrate;

using the photoresist layer as a hard mask to perform an etching process to the low k dielectric layer; and

performing a wet stripping process;

wherein the passivation layer is used to inhibit the formation of Si—OH bonds that absorb moisture in the low k dielectric layer during the wet stripping process to avoid deterioration of dielectric characteristics of the low k dielectric layer.

11. The method of claim 10 wherein the substrate is silicon substrate provided by a silicon wafer.

12. The method of claim 10 wherein the low k dielectric layer is composed of HSQ hydrogen, MSQ, H-PSSQ, M-PSSQ, P-PSSQ or HOSP.

13. The method of claim 12 wherein the low k material is formed on the substrate by performing a chemical vapor deposition (CVD) process or a spin-on process.

14. The method of claim 10 wherein the surface treatment is a plasma treatment.

15. The method of claim 14 wherein the plasma treatment is performed in a nitrogen-containing environment to form the passivation layer on the surface of the low k dielectric layer.

16. The method of claim 15 wherein the nitrogen-containing environment comprises nitrous oxide (N 2 O), nitric oxide (NO), or ammonia (NH 3 ).

17. The method of claim 16 wherein the plasma treatment utilizes a radio frequency (RF) of the plasma treatment having a power of about 100 to 300 Watts (W), a process pressure that is between 10 −3 -10 −6 Torr, a process time that is less than 20 minutes, and a process temperature of the substrate that is less than 250° C.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →