Method for determining valid bytes for multiple-byte burst memories
View Patent ↗A memory controller for a multi-byte burst memory device may control access to memory based on parameters set up by a client. These parameters may include a byte address and a byte count that indicates the number of bytes the client is requesting from memory. These values, and an integer representing the number of bytes in a burst-accessed word, may be operated on to produce a word that may be used to identify valid bytes in the burst-accessed word.
1. A method for determining valid bytes in an m-byte word accessed from a burst memory, comprising:
receiving a plurality of access parameters;
generating an m-bit enable word from the access parameters and a value of m, said m-bit enable word including at least one valid bit corresponding to at least one valid byte in the m-byte word; and
making a client request to memory;
wherein the access parameters from which the m-bit enable word is generated include a first address and a byte count value indicating a number of bytes in said client request to memory; and
wherein generating the m-bit enable word comprises
truncating a portion of the first address to produce an n-bit word,
generating an enable value from the n-bit word, the byte count value, and the m value,
generating an m-bit pre-shifted enable word from the enable value and the m, and
shifting the bits in the m-bit pre-shifted enable word by a value of the n-bit word.
2. The method of claim 1 , wherein the n value equals a base two logarithm of the m value minus one, and said n-bit word comprises a plurality of bits between and including a least significant bit and a bit in position n in the first address.
3. The method of claim 1 , further comprising:
in response to the byte count value and the enable value, determining whether an access to memory satisfies a client request which generated the access.
4. The method of claim 1 , further comprising:
generating a second address for a subsequent access to memory from the first address and the enable value.
5. The method of claim 1 , wherein the value of m is thirty-two.
6. A memory controller comprising:
a data input to receive a plurality of access parameters from a client device and an access bytes value indicating a number of bytes in an m-byte burst word from a memory device; and
an enable circuit to determine at least one valid byte in the m-byte burst word in response to the plurality of access parameters and the access bytes value;
wherein the plurality of access parameters in response to which the at least one valid byte in the m-byte burst word is determined include a first address and a byte count value indicating a number of bytes in a client request to memory; and
wherein the enable circuit determines the at least one byte in the m-byte burst word by
truncating a portion of the first address to produce an n-bit word,
generating an enable value from the n-bit word, the byte count value, and a value of m,
generating an m-bit pre-shifted enable word from the enable value and the m value, and
shifting the bits in the m-bit pre-shifted enable word by a value of the n-bit word.
7. The memory controller of claim 6 , further comprising:
an enable word generator to generate an enable word including at least one valid bit corresponding to the at least one valid byte in the burst word.
8. The memory controller of claim 7 , wherein the burst word comprises an m-byte word and the enable word comprises an m-bit word.
9. A system, comprising:
a memory device comprising a plurality of memory elements, each memory element having an associated address;
a client device;
a bus to pass data between the memory device and the client device; and
a memory controller to control an access by the client device to an m-byte burst word in the memory device over the bus, said memory controller operating to receive a plurality of access parameters from the client device and determine at least one valid byte in the m-byte word in response to the plurality of access parameters and a value of m;
wherein the memory controller comprises an enable word generator to generate an enable word including at least one valid bit corresponding to the at least one valid byte in the burst word;
wherein the memory controller is operative to receive a client request to memory;
wherein the plurality of access parameters, from which the at least one valid byte is determined, include a first address and a byte count value indicating a number of bytes in said client request to memory; and
wherein the enable word generator generates the enable word by
truncating a portion of the first address to produce, an n-bit word,
generating an enable value from the n-bit word, the byte count value, and a value of m,
generating an m-bit pre-shifted enable word from the enable value and the m value, and
shifting the bits in the m-bit pre-shifted enable word by a value of the n-bit word.
10. The system of claim 9 , wherein the memory controller is operative to determine a second address for a subsequent access for the plurality of access parameters.
11. The system of claim 10 , wherein the client is operative to store the second address.
12. The system of claim 9 , wherein the memory device is a burst memory device.
13. The system of claim 9 , wherein the memory controller is operative to determine whether the access is a last access required to satisfy a client request.
14. The system of claim 9 , wherein the bus comprises a read bus and a write bus.
15. Apparatus, including instructions residing on a machine-readable medium, for determining valid bytes in an m-byte word accessed from a burst memory, said instructions causing the machine to:
receive a plurality of access parameters; and
generate an m-bit enable word from the access parameters and the m value, said m-bit enable word including at least one valid bit corresponding to at least one valid byte in the m-byte word;
wherein the access parameters, from which the m-bit enable word is generated, include a first address and a byte count value indicating a number of bytes in a client request to memory; and
wherein the instructions to generate the m-bit enable word comprise instructions causing the machine to
truncate a portion of the first address to produce an n-bit word,
generate an enable value from the n-bit word, the byte count value, and the m value,
generate an m-bit pre-shifted enable word from the enable value and the m value, and
shift the bits in the m-bit pre-shifted enable word by a value of the n-bit word.
16. The apparatus of claim 15 , wherein the n value equals a base two logarithm of the m value minus one, and said n-bit word comprises a plurality of bits between and including a least significant bit and a bit in position n in the first address.
17. The apparatus of claim 15 , further comprising instructions that cause the machine to:
determine whether an access to memory satisfies a client request in response to the byte count value and the enable value.
18. The apparatus of claim 15 , further comprising instructions that cause the machine to:
generate a second address for a subsequent access to memory from the first address and the enable value.
19. The apparatus of claim 15 , wherein the value of m is thirty-two.