Patent Assignment
Reel/Frame 036942/0213
Assignment of Assignor's Interest
Recorded: 2015-10-23
Pages: 30
Assignor
EMULEX CORPORATION
Executed: 2015-08-31
Assignee
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
1 YISHUN AVENUE 7, SINGAPORE, 768923, SINGAPORE
Covered Properties
(299)
A Memory Buffer System Using a Single Pointer to Reference Multiple Associated Data
Patent:
5,860,149 →
Application:
08/484,592 →
Burst Broadcasting on a Peripheral Component Interconnect Bus
Patent:
5,634,138 →
Application:
08/488,035 →
Computer Network Interface for Direct Mapping of Data Transferred Between Applications on Different Host Computers from Virtual Addresses to Physical Memory Addresses
Patent:
6,094,712 →
Application:
08/762,186 →
Fibre Channel Switching Fabric
Patent:
6,185,203 →
Application:
08/801,471 →
Linked Caches Memory for Storing Units of Information
Patent:
5,745,727 →
Application:
08/843,315 →
Methods and Apparatus for Fibre Channel Interconnection of Private Loop Devices
Patent:
6,118,776 →
Application:
08/907,385 →
Full-Duplex Communication Processor Which Can Be Used for Fibre Channel Frames.
Patent:
6,005,849 →
Application:
08/937,066 →
Buffering Data That Flows Between Buses Operating at Different Frequencies
Patent:
6,047,339 →
Application:
08/957,856 →
System and Method for Scheduling Message Transmission and Processing in a Digital Data Network
Patent:
6,795,442 →
Application:
09/065,115 →
System and Method for Regulating Message Flow in a Digital Data Network
Patent:
6,570,850 →
Application:
09/065,118 →
System for Transfering Information Between Devices Over Virtual Circuit Established Therebetween Using Computer Network a Computer Network
Patent:
5,991,818 →
Application:
09/067,533 →
Method and Apparatus for Control of Soft Handoff Usage in Radiocommunication Systems
Patent:
6,560,205 →
Application:
09/071,275 →
Method of Mapping Fibre Channel Frames Based on Control and Type Header Fields
Patent:
6,098,125 →
Application:
09/071,276 →
Automatic Loop Segment Failure Isolation
Patent:
6,101,166 →
Application:
09/071,288 →
Programmable Error Control Circuit
Patent:
6,167,026 →
Application:
09/071,431 →
Scalable Hub
Patent:
6,282,188 →
Application:
09/071,508 →
Hub Port Without Jitter Transfer
Patent:
6,064,679 →
Application:
09/071,632 →
Automatic Isolation in Loops
Patent:
6,188,668 →
Application:
09/071,678 →
Elimination of Invalid Data in Loop Network
Patent:
6,226,269 →
Application:
09/071,930 →
Hub Port with Constant Phase
Patent:
6,157,652 →
Application:
09/071,932 →
Method and System for Programming Firmware Over a Computer Network
Patent:
6,199,194 →
Application:
09/161,158 →
Node Insertion and Removal in a Loop Network
Patent:
6,215,775 →
Application:
09/177,550 →
Automatic Detection of 8B/10B Data Rates
Patent:
6,158,014 →
Application:
09/204,669 →
An Efficient Transmission Buffer Management System
Patent:
6,041,397 →
Application:
09/229,464 →
Sanitizing Fibre Channel Frames
Patent:
6,226,299 →
Application:
09/234,231 →
Fibre Channel Switching Fabric
Patent:
6,904,053 →
Application:
09/330,398 →
Fibre Channel Switching System
Patent:
7,688,735 →
Application:
09/330,755 →
Distributed Switch and Connection Control Arragement and Method for Digital Communications Network
Patent:
6,791,948 →
Application:
09/347,709 →
Variable Access Fairness in a Fibre Channel Arbitrated Loop
Patent:
6,459,701 →
Application:
09/370,096 →
Automatic Loop Segment Failure Isolation
Patent:
6,201,787 →
Application:
09/398,520 →
Automatic Isolation in Loops
Patent:
6,289,002 →
Application:
09/398,523 →
High Performance Digital Loop Diagnostic Technology
Patent:
6,888,800 →
Application:
09/436,620 →
Interconnect System for Fibre Channel Arbitrated Loop Including Private Loop Devices
Patent:
6,470,007 →
Application:
09/611,173 →
Detecting and Counting Node Port Loop Initialization Origination
Patent:
6,687,219 →
Application:
09/640,564 →
Detecting and Counting Open Ordered Sets Originating from an Attached Node Port
Patent:
6,483,843 →
Application:
09/687,259 →
Method for Determining Valid Bytes for Multiple-Byte Burst Memories
Patent:
6,904,505 →
Application:
09/687,526 →
Old-Port Node Detection and Hub Port Bypass
Sanitizing Fibre Channel Frames
Hardware Initialization with or Without Processor Intervention
Protocol Stack for Linking Storage Area Networks Over an Existing Lan, Man, or Wan
Method and System for Verifying the Hardware Implementation of Tcp/Ip
Data Formatter for Shifting Data to Correct Data Lanes
System for Communication with a Storage Area Network
Separable Cyclic Redundancy Check
Patent:
6,961,893 →
Application:
10/113,147 →
Receiving Data from Interleaved Multiple Concurrent Transactions in a Fifo Memory Having Programmable Buffer Zones
Tracking Deferred Data Transfers on a System-Interconnect Bus
Phase-Locked Loop (Pll) Circuit for Selectively Correcting Clock Skew in Different Modes
Direct Memory Access (Dma) Transfer Buffer Processor
Methods and Apparatus for Fibre Channel Interconnection of Private Loop Devices
Apparatus and Methods for Transmitting Data at High Speed Using Tcp/Ip
Apparatus and Methods for Receiving Data at High Speed Using Tcp/Ip
Systems and Methods for High Speed Data Transmission Using Tcp/Ip
Systems and Methods for Implementing Host-Based Security in a Computer Network
Methods and Apparatus for Partially Reordering Data Packets
Re-Programmable Finite State Machine
Method and Apparatus for Improving Noise Immunity in a Ddr Sdram System
Line Rate Buffer Using Single Ported Memories for Variable Length Packets
Patent:
6,901,496 →
Application:
10/264,580 →
Structure and Method for Maintaining Ordered Linked Lists
System with Multiple Path Fail Over, Fail Back and Load Balancing
Network Configuration Synchronization for Hardware Accelerated Network Protocol
Message Logging
Methods and Apparatus for Fibre Channel Interconnection of Private Loop Devices
Supercharge Message Exchanger
Direct Memory Access Controller System with Message-Based Programming
Shared Memory Management Utilizing a Free List of Buffer Indices
Structure and Method for Managing Available Memory Resources
Sanitizing Fibre Channel Frames
Abstracted Node Discovery
Phase-Locked Loop (Pll) Circuit for Selectively Correcting Clock Skew in Different Modes
Method of Queuing Fibre Channel Receive Frames
Patent:
6,728,861 →
Application:
10/382,728 →
System and Method for Regulating Message Flow in a Digital Data Network
Direct Data Placement
Local Emulation of Data Ram Utilizing Write-Through Cache Hardware Within a Cpu Module
Hardware Assisted Firmware Task Scheduling and Management
Virtual Peripheral Component Interconnect Multiple-Function Device
Avoiding Port Collisions in Hardware-Accelerated Network Protocol
Patent:
7,673,074 →
Application:
10/421,495 →
Reverse Message Writes and Reads
Patent:
7,028,131 →
Application:
10/422,581 →
Loop Network Hub Using Loop Initialization Insertion
Hot Swap Compact Pci Power Supply
Dynamically Self-Adjusting Polling Mechanism
Memory Data Interface
Method and Apparatus for Local and Distributed Data Memory Access ("Dma") Control
Apparatus for Performing and Coordinating Data Storage Functions
Application:
10/569,322 →
Publication:
US 2008/0172532
Integrated-Circuit Implementation of a Storage-Shelf Router and a Path Controller Card for Combined Use in High-Availability Mass-Storage-Device Shelves That May Be Incorporated Within Disk Arrays
Sparse and Non-Sparse Data Management Method and System
Read/Write Command Buffer Pool Resource Management Using Read-Path Prediction of Future Resources
Methods and Apparatus for Switching Fibre Channel Arbitrated Loop Devices
Methods and Apparatus for Device Access Fairness in Fibre Channel Arbitrated Loop Systems
Methods and Apparatus for Device Zoning in Fibre Channel Arbitrated Loop Systems
Methods and Apparatus for Switching Fibre Channel Arbitrated Loop Systems
Methods and Apparatus for Trunking in Fibre Channel Arbitrated Loop Systems
Virtual Interface Over a Transport Protocol
Patent:
7,953,876 →
Application:
10/651,426 →
System and Method for Direct Memory Access from Host Without Processor Intervention Wherein Automatic Access to Memory During Host Start Up Does Not Occur
Multi-Channel Memory Access Arbitration Method and System
Integrated network interface supporting multiple data transfer protocols
Application:
10/653,767 →
Publication:
US 2005/0066045
Generalized Queue and Specialized Register Configuration for Coordinating Communications Between Tightly Coupled Processors
Integrated-Circuit Implementation of a Storage-Shelf Router and a Path Controller Card for Combined Use in High-Availability Mass-Storage-Device Shelves That May Be Incorporated Within Disk Arrays, and a Storage-Shelf-Interface Tunneling Method and System
Integrated-Circuit Implementation of a Storage-Shelf Router and a Path Controller Card for Combined Use in High-Availability Mass-Storage-Device Shelves and That Support Virtual Disk Formatting
Method and Apparatus for Network Interface Card Load Balancing and Port Aggregation
Patent:
41,397 →
Application:
10/704,464 →
Methodology and Apparatus for Solving Lockup Conditions While Trunking in Fibre Channel Switched Arbitrated Loop Systems
Patent:
7,403,481 →
Application:
10/769,580 →
Shared Input/Output Load-Store Architecture
Method of Writing Non-Volatile Memory That Avoids Corrupting the Vital Initialization Code
Prerequisite-Based Scheduler
Apparatus and Method for Sharing I/O Endpoints Within a Load Store Fabric by Encapsulation of Domain Information in Transaction Layer Packets
Switching Apparatus and Method for Providing Shared I/O Within a Load-Store Fabric
Switching Apparatus and Method for Providing Shared I/O Within a Load-Store Fabric
Management of Error Conditions in High-Availability Mass-Storage-Device Shelves by Storage-Shelf Routers
System and Method for Scheduling Message Transmission and Processing in a Digital Data Network
Hardware Initialization with or Without Processor Intervention
Digital Loop Diagnostic Loop Initialization Sequencing.
Digital Loop Diagnostic Port Control Monitor
Digital Loop Diagnostic Port Test Before Insertion
Switching Apparatus and Method for Link Initialization in a Shared I/O Environment
Managing Configuration Data in a Flash Configuration Space in Flash Memory Within a Host Interface Port
Legacy-Compatible Extended Command Input-Output Control Block
Supercharge Message Exchanger
Interrupt Notification Block
Device-Independent Control of Storage Hardware Using Scsi Enclosure Services
Integrated-Circuit Implementation of a Storage-Shelf Router and a Path Controller Card for Combined Use in High-Availability Mass-Storage-Device Shelves That May Be Incorporated Within Disk Arrays
Monitoring Detection and Removal of Malfunctioning Devices from an Arbitrated Loop
Discovery and Configuration of Devices Across an Ethernet Interface
Host Buffer Queue for Temporary Storage of Incoming Data
Application:
11/039,446 →
Publication:
US 2006/0161733
Controlling Device Access Fairness in Switched Fibre Channel Fabric Loop Attachment Systems
Dynamically Controlling Fair Access to a System Packet Interface Attached Switch Enclosure
Buffering Registered State Change Notifications to Reduce Traffic During Large Fabric Changes
Apparatus and Method for Port Polarity Initialization in a Shared I/O Device
Prevention of Head of Line Blocking in a Multi-Rate Switched Fibre Channel Loop Attached System
Direct Memory Access Controller System with Message-Based Programming
Tunneling Sata Targets Through Fibre Channel
Method and Apparatus for Sata Tunneling Over Fibre Channel
Programming of Configuration Serial Eeprom via an External Connector
Fibre Channel Switching Fabric Hub
Fibre Channel Switching Fabric Router
Fibre Channel Switching Fabric Port Control
Stacking Series of Non-Power-of-Two Frame Buffers in a Memory Array
Method for Synchronized Trunk Failover and Failback in a Fc-Al Switching Environment
Input/Output Router for Storage Networks
Receive Coalescing and Automatic Acknowledge in Network Interface Controller
Automated Notification of Software Installation Failures
Message Signaled Interrupt Extended (Msi-X) Auto Clear and Failsafe Lock
Automated logical unit creation and assignment for storage networks
Application:
11/240,022 →
Publication:
US 2007/0079097
Switching Apparatus and Method for Providing Shared I/O Within a Load-Store Fabric
System Method and Software for User Customizable Device Insertion
N_Port Virtualization Driver-Based Application Programming Interface and Split Driver Implementation
Apparatus for performing I/O sharing & virtualization
Application:
11/353,698 →
Publication:
US 2007/0192518
Method for Tracking and Storing Time to Complete and Average Completion Time for Storage Area Network I/O Commands
Method and Apparatus for Auto-Protocol Discrimination Between Fibre Channel, Sas and Sata Devices
Supercharge Message Exchanger
Data Path Differentiator for Pre-Emphasis Requirement Determination or Slot Identification
Methods and Apparatus for Fibre Channel Interconnection of Private Loop Devices
Methodology for manipulation of SATA device access cycles
System and Method for Virtualizing Pcie Devices
Lock and Release Mechanism for Out-of-Order Frame Prevention and Support of Native Command Queueing in Fc-Sata
Fibre Channel Over Ethernet
Virtual drive mapping
Application:
11/636,108 →
Publication:
US 2008/0140930
Programmable Bridge Header Structures
Apparatus for performing storage virtualization
Chip Overheating Protection
Autonomous Mapping of Protected Data Streams to Fibre Channel Frames
MULTI-PROTOCOL CONTROLLER THAT SUPPORTS PCIe, SAS AND ENHANCED ETHERNET
Label Switched Routing in Sas Expanders
Expander-Based Solution to the Dynamic Stp Address Problem
Systems and Methods for Asic Power Consumption Reduction
Cache Pollution Avoidance
Sas Expander-Side Optimization for the Re-Discovery Process
Isolation of Unverified Devices in a Sas Expander
Method and Interface for Access to Memory Within a First Electronic Device by a Second Electronic Device
Global shared memory switch
Application:
11/824,511 →
Publication:
US 2008/0028157
Allocation-Unit-Based Virtual Formatting Methods and Devices Employing Allocation-Unit-Based Virtual Formatting Methods
Method and System for Efficient Queue Management
High Performance Ethernet Networking Utilizing Existing Fibre Channel Arbitrated Loop Hba Technology
Enabling Sas Expander Loops for Increased Fairness and Performance
Sas Reference Phys for Virtualization and Traffic Isolation
Efficient Processing of Groups of Host Access Requests That May Include Zero Length Requests
High Performance Ethernet Networking Utilizing Existing Fibre Channel Fabric Hba Technology
Network Adapter Based Zoning Enforcement
Sas Expander Based Persistent Connections
Self Checking Encryption and Decryption Based on Statistical Sampling
Application:
11/966,890 →
Publication:
US 2010/0023748
Data Bus Efficiency via Cache Line Usurpation
Detection and Configuration of Sas/Sata Connection
Snooping in Sas Expander Networks
Alignment-Unit-Based Virtual Formatting Methods and Devices Employing the Methods
Flagging of Port Conditions in High Speed Networks
Virtualization Bridge Device
Patent:
7,979,592 →
Application:
12/028,801 →
Methods, Apparatus, and Systems for Integrated Management, Graphics and I/O Control of Server Systems
Virtual Universal Asynchronous Receiver Transmitter for Server Systems
Hardware Cursor Snooping
Methods and Apparatus for Non-Intrusive Capturing of Frame Buffer Memory Information for Remote Display
Generation of Simulated Errors for High-Level System Validation
System and Method for Enabling Multiple Processors to Share Multiple Sas Wide Ports
Secure Configuration of Authentication Servers
Switching Apparatus and Method for Link Initialization in a Shared I/O Environment
Restore PCIe Transaction ID on the Fly
Off-Chip Interface for External Routing
Application:
12/135,017 →
Publication:
US 2009/0303990
Method for Re-Sequencing Commands and Data Between a Master and Target Devices Utilizing Parallel Processing
Methods and Apparatus for Fibre Channel Interconnection of Private Loop Devices
Hardware Switch for Hypervisors and Blade Servers
Combined Fcoe Network Device
Dynamically Adjustable Arbitration Scheme
Application:
12/207,380 →
Publication:
US 2010/0064072
Method to Improve the Performance of a Computer Network
Address Identifier Scaling in Converged Networks
Large Frame Path Mtu Discovery and Communication for Fcoe Devices
Method and System for Controlling Traffic Over a Computer Network
Stateless Fibre Channel Sequence Acceleration for Fibre Channel Traffic Over Ethernet
Client/Server Authentication Over Fibre Channel
System and Method for Data Protection Against Power Failure During Sector Remapping
System and Method for Sector Remapping
Methods and Apparatus for Fibre Channel Interconnection of Private Loop Devices
Method for Verifying Correct Encryption Key Utilization
Computer System Input/Output Management
System and Method for Direct Communications Between Fcoe Devices
Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes
Integrated-Circuit Implementation of a Storage-Shelf Router and a Path Controller Card for Combined Use in High-Availability Mass-Storage-Device Shelves and That Support Virtual Disk Formatting
Sas Expander-Based Sas/Sata Bridging
Accelerated Sockets
Power Management for Input/Output Devices by Creating a Virtual Port for Redirecting Traffic
Fibre Channel Switching System
Inline PCI-IOV Adapter
Out of Band Data Transfer Over Optical Connections
Programmable Bridge Header Structures
Fibre Channel Switching Fabric Port Control
Fibre Channel Switching Fabric Port Control
Systems and Method for Routing Data
Roce Packet Sequence Acceleration
Data Path Differentiator for Pre-Emphasis Requirement or Slot Identification
Method for Parsing Network Packets Having Future Defined Tags
System and Method for Interconnecting Ethernet and Fibre Channel
System and method for routing data
System and Method for Interconnecting Multiple Communication Interfaces
Interconnect System and Method for Ethernet Networks
System and method for routing data
Out of Band Data Transfer Over Optical Connections
Adaptive Receive Path Learning to Facilitate Combining Tcp Offloading and Network Adapter Teaming
Positive Feedback Ethernet Link Flow Control for Promoting Lossless Ethernet
Soft Error Protection for Content Addressable Memory
Patent:
9,146,808 →
Application:
13/749,669 →
Reducing Write I/O Latency Using Asynchronous Fibre Channel Exchange
Using Pci-E Extended Configuration Space to Send Ioctls to a Pci-E Adapter
Power Management for Input/Output Devices
Network Virtualization via I/O Interface
Application:
13/802,413 →
Publication:
US 2014/0282551
Data Transmission Scheduling
Application:
13/842,678 →
Publication:
US 2014/0281022
Low-Latency Packet Receive Method for Networking Devices
Direct Push Operations and Gather Operations
Large Frame Path Mtu Discovery and Communication for Fcoe Devices
Application:
13/846,838 →
Publication:
US 2013/0223281
Method and System for Communications-Stack Offload to a Hardware Controller
Application:
13/969,975 →
Publication:
US 2015/0052280
Secure Configuration of Authentication Servers
Generation of Simulated Errors for High-Level System Validation
Guest-Based Quality of Service for iSCSI
System and Method for Debugging
Application:
14/083,819 →
Publication:
US 2015/0139249
Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes
Restore Pcie Transaction Id on the Fly
Computer System Input/Output Management
Application:
14/093,926 →
Publication:
US 2014/0089735
Remote Management System
Interconnect system and method for ethernet networks
Sas Expander Based Persistent Connections
Network Adapter Based Zoning Enforcement
Roce Packet Sequence Acceleration
Generation of Simulated Errors for High-Level System Validation
System and Method for Adding Error Protection Capability to a Digital Logic Circuit
Application:
14/225,816 →
Publication:
US 2015/0279486
Out of Band Data Transfer Over Optical Connections
Application:
14/255,542 →
Publication:
US 2014/0255041
Automatic Derivation of System Performance Metric Thresholds
Application:
14/271,975 →
Publication:
US 2015/0281008
Fibre Channel Over Ethernet
Application:
14/272,785 →
Publication:
US 2014/0241379
Data Path Differentiator for Pre-Emphasis Requirement Determination or Slot Identification
Application:
14/281,394 →
Publication:
US 2014/0258585
Systems and Method for Routing Data
Application:
14/292,068 →
Publication:
US 2014/0270763
Priority Queueing for Low Latency Storage Networks
Patent:
9,983,801 →
Application:
14/309,875 →
System and Method for Managing Logins in a Network Interface
System and Method for Managing Storage Transactions in a Network Interface
Application:
14/316,233 →
Publication:
US 2015/0281001
System and Method for Error Recovery in an Asynchronous FIFO
Application:
14/316,435 →
Publication:
US 2015/0378812
Message Passing for Low Latency Storage Networks
Patent:
9,680,931 →
Application:
14/329,379 →
Systems with Virtual Universal Asynchronous Receiver Transmitter and Methods Therefor
System and Method for Interconnecting Multiple Communication Interfaces
Application:
14/454,440 →
Publication:
US 2014/0362860
Hash Tag Load Balancing
Accelerated Sockets
Method for Parsing Network Packets Having Future Defined Tags
Power Management for Input/Output Devices
Application:
14/494,741 →
Publication:
US 2015/0012771
Network Adapter Based Zoning Enforcement
Application:
14/515,024 →
Publication:
US 2015/0030030
Secure Configuration of Authentication Servers
Data Bus Efficiency via Cache Line Usurpation
Registrationless Transmit Onload Rdma
Application:
14/523,840 →
Publication:
US 2016/0026605
System and Method for Interconnecting Physical Channels
Dynamic Rdma Queue On-Loading
Application:
14/536,494 →
Publication:
US 2016/0026604
Stateless Fibre Channel Sequence Acceleration for Fibre Channel Traffic Over Ethernet
Cache Prefill of Cache Memory for Rapid Start Up of Computer Servers in Computer Networks
Patent:
9,547,598 →
Application:
14/588,118 →
Roce Packet Sequence Acceleration
Method for Verifying Correct Encryption Key Utilization
Systems and Method for Routing Data
Application:
14/669,401 →
Publication:
US 2015/0200851
Positive Feedback Ethernet Link Flow Control for Promoting Lossless Ethernet
Application:
14/680,451 →
Publication:
US 2015/0215224
Data Bus Efficiency Via Cache Line Usurpation
Stateless Fibre Channel Sequence Acceleration for Fibre Channel Traffic Over Ethernet
Application:
14/695,212 →
Publication:
US 2015/0229568
Apparatus for Performing Storage Virtualization
Application:
14/695,272 →
Publication:
US 2015/0227325
Interconnect System and Method for Ethernet Networks
Application:
14/699,012 →
Publication:
US 2015/0263938
Monitoring in Switch Networks
Application:
14/704,061 →
Publication:
US 2015/0236937
Restore PCIe Transaction ID On The Fly
Application:
14/728,676 →
Publication:
US 2015/0293865
Priority Queueing for Flash-Based Storage Networks
Application:
61/880,919 →
Registrationless Transmit Onload Rdma
Application:
62/030,057 →
Cache Prefill, Protected Write, Cache Invalidate, and Cache Autocopy Messages for Low Latency Storage Networks
Application:
62/087,231 →
Operating System Software Install and Boot Up from a Storage Area Network Device
Application:
62/101,902 →
Reliable Remote Direct Memory Access (Rdma) Communication
Application:
62/104,635 →
Queue Pair State Transition Speedup
Application:
62/114,191 →
Host Bus Adapter with Built-in Storage for Local Boot-Up
Application:
62/144,329 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 17, 2014
From: EMULEX DESIGN AND MANUFACTURING CORPORATION
To: EMULEX CORPORATION
Reel/Frame 032087/0842 →
Patent Security Agreement
Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
Termination and Release of Security Interest in Patents
Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
Merger
Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
Corrective Assignment to Correct the Execution Date Previously Recorded at Reel: 047422 Frame: 0464. Assignor(S) Hereby Confirms the Merger.
Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →