System for communication with a storage area network
View Patent ↗A system enables communication between a first network having a first network protocol and a second network having a second network protocol. At least one of the first and second networks is a storage area network. The system includes first and second data ports for receiving, from the first network, input data and state information respectively. A microsequencer is configured to translate the input data, which is expressed in the first network protocol, into corresponding data expressed in the second network protocol. This translation is performed in part on the basis of the state information.
1. A system for enabling communication between a first network having a first network protocol and a second network having a second network protocol, the second network being a storage area network, said system comprising:
a first data port for receiving first input data and first state information from said first network, said first input data being expressed in said first network protocol;
a second data port for receiving second input data and second state information from said second network, said second input data being expressed in said second network protocol;
a first microsequencer system configured to translate said second input data into corresponding data expressed in said first network protocol on the basis of said first state information, the first microsequencer system including one or more microsequencers configured to cooperate in translating said second input data into corresponding data expressed in said first network protocol;
a second microsequencer system configured to translate said first input data into corresponding data expressed in said second network protocol on the basis of said second state information, the second microsequencer system including one or more microsequencers configured to cooperate in translating said first input data into corresponding data expressed in said second network protocol; and
an instruction memory accessible to each of the microsequencers of the first and second microsequencer systems, said instruction memory having a plurality of instruction words, each of said instruction words forming a Very Long Instruction Word (VLTW) having a plurality of instruction fields executable in parallel by different functional units of each of the microsequencers to enable the microsequencers to execute a plurality of instructions in a single instruction cycle, the instruction memory being loadable via a processor interface to make the microsequencers programmable to accommodate different first and second network protocols.
2. The system of claim 1 , further comprising:
an instruction-memory pointer for identifying a selected instruction word in said instruction memory.
3. The system of claim 1 , further comprising a translation-memory accessible to each of the microsequencers of said first and second microsequencer systems, said translation-memory having
a translation-memory address, and
a translation-memory element corresponding to said translation-memory address, said translation-memory element including data for musing an instruction-memory pointer to jump to a selected instruction word.
4. The system of claim 3 , wherein said translation-memory element is configured to include an absolute address of said selected instruction word.
5. The system of claim 3 , wherein said translation-memory element is configured to include an offset from a current instruction word to said selected instruction word.
6. The system of claim 3 , further comprising a translation-memory pointer for indirectly causing said instruction-memoiy pointer to jump to a selected instruction memory address.
7. The system of claim 6 , wherein said translation-memory pointer is configured to identify a selected translation-memory address corresponding to a translation memory element that contains data indicative of said selected instruction-memory address.
8. The system of claim 1 , further comprising a translation-memory having:
a translation-memory address;
a first translation-memory element corresponding to said translation-memory address, said first translation-memory element including data for causing an instruction-memory pointer to jump to a first instruction word;
a second translation-memory element corresponding to said translation-memory address, said second translation-memory element including data for causing said instruction-memory pointer to jump to a second instruction word; and
a selector for selecting said first translation-memory element.
9. The system of claim 8 , whei:ein said selector comprises a multiplexer having
a first multiplexer input for receiving data indicative of content of said first translation-memory element;
a second multiplexer input for receiving data indicative of content of said second translation-memory element;
an output providing data selected from at least said first multiplexer input and said second multiplexer input; and
a control input for controlling data provided at said output.
10. The system of claim 1 , further comprising an output port in communication with said second microsequencer system for providing said corresponding data to said second network.
11. The system of claim 1 , wherein said first and second data ports and said first and second niicrosequencer systems are integrated into one integrated circuit.