IP Library Granted Patent US 8,134,918
Granted Patent B2
US 8,134,918 · App. 11/147,041 · Granted Mar 13, 2012

Fibre channel switching fabric hub

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Quick Facts
Patent No.
US 8,134,918
App. No.
11/147,041
Granted
Mar 13, 2012
Kind
B2
Abstract

The Fiber Channel standard was created by the American National Standard for Information Systems (ANSI) X3T11 task group to define a serial I/O channel for interconnecting a number of heterogeneous peripheral devices to computer systems as well as interconnecting the computer systems themselves through optical fiber and copper media at gigabit speeds (i.e., one billion bits per second). Multiple protocols such as SCSI (Small Computer Serial Interface), IP (Internet Protocol), HIPPI, ATM (Asynchronous Transfer Mode) among others can concurrently utilize the same media when mapped over Fiber Channel. A Fiber Channel Fabric is an entity which transmits Fiber Channel frames between connected Node Ports. The Fiber Channel fabric routes the frames based on the destination address as well as other information embedded in the Fiber Channel frame header. Node Ports are attached to the Fiber Channel Fabric through links.

Claims (15)

1. A hub for interconnecting a plurality of communications channels on a loop comprising:

a port connected to a Fibre channel fabric, the port including a transmit SERDES and a receiver SERDES;

a first hub circuit, the first hub circuit including an input connected to the transmit SERDES of the port, the first hub circuit including a port bypass circuit coupled between the input and an output of the first hub circuit, a first interface converter module coupled to the first hub circuit, the first interface converter module being configured to couple to a first device,

a second hub circuit, the second hub circuit including an input, the second hub circuit including a port bypass circuit coupled between the input and an output of the second hub circuit, a second interface converter module coupled to the second hub circuit, the second interface converter module being configured to couple to a second device, the input of the second hub circuit being serially connected to the output of first hub circuit,

the output of the second hub circuit being connected to the receiver SERDES of the port, and

control logic connected to the first hub circuit and second hub circuit whereby the control logic is configured to allow a transmitted frame to bypass the first or second device by transmitting the flame through the port bypass circuit of one or more of the first and second hub circuits.

2. A hub as claimed in claim 1 wherein at least one of the interface converter modules comprises a gigabit interface converter.

3. A hub as claimed in claim 1 wherein the hub can be managed via control signals.

4. A hub as claimed in claim 1 further including a third hub circuit, the third hub circuit including an input and a third port bypass circuit coupled between the input and an output of the third hub circuit, a third interface converter module coupled to the third hub circuit, the third interface converter module being adapted to couple to a third device, the input of the third hub circuit being serially connected to the output of second hub circuit.

5. A hub as claimed in claim 1 further including a fourth hub circuit, the fourth hub circuit including an input and a fourth port bypass circuit coupled between the input and an output of the fourth hub circuit, a fourth interface converter module coupled to the fourth hub circuit, the fourth interface converter module being adapted to couple to a fourth device, the input of the fourth hub circuit being serially connected to the output of third hub circuit.

6. A hub as claimed in claim 1 wherein the port couples to a switch.

7. A hub as in claim 1 , wherein the hub circuits include clock recovery circuits.

8. A hub as in claim 6 , wherein the plurality of port bypass circuits are connected to the switch through an Endec.

9. A hub as in claim 1 , wherein the plurality of port bypass circuits are coupled to a fabric control processor through a register for controlling said plurality of port bypass circuits.

10. A hub as in claim 6 , wherein the switch is an 8×8 crosspoint switch.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: EMULEX CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036942/0213 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2014
From: EMULEX DESIGN AND MANUFACTURING CORPORATION
To: EMULEX CORPORATION
Reel/Frame 032087/0842 →