SYSTEM AND METHOD FOR ADDING ERROR PROTECTION CAPABILITY TO A DIGITAL LOGIC CIRCUIT
A system and method for adding error protection capability to a digital logic circuit, for example including random storage logic. Various aspects of the present disclosure, for example, comprise providing error protection against soft errors that occur during operation of digital logic circuitry.
1 . A method of producing an electronic device with on-board error detection, the method comprising:
generating a plurality of parity protect groups, where each of the plurality of parity protect groups comprises:
a number of storage elements under test, each of which is coupled to a same set of control signal inputs comprising: a same clock net, a same clear net, and a same preset net;
a parity test storage element coupled to said same set of control signal inputs; and
a parity test output;
generating a report point comprising a report point storage element that outputs parity test results;
logically combining each of the respective parity test outputs of each of the plurality of parity protect groups at an input of the report point storage element; and
fabricating the electronic device comprising said plurality of parity protect groups and said report point,
wherein:
the plurality of parity protect groups are all associated with said same set of control signal inputs; and
the respective number of storage elements under test of each of the plurality of parity protect groups is an odd number.
2 . The method of claim 1 , wherein each of the plurality of parity protect groups comprises an XOR tree that outputs the parity test output and receives as inputs an output from the parity test storage element of the parity protect group and respective outputs from each of the storage elements under test of the parity protect group.
3 . The method of claim 1 , comprising, prior to said generating a plurality of parity protect groups, determining a maximum number of storage elements under test for each of the plurality of parity protect groups, and wherein the respective number of storage elements under test for each of the plurality of parity protect groups is no more than the determined maximum number.
4 . The method of claim 1 , wherein at least 75% of all parity protect groups of the electronic device that correspond to a respective non-null preset net have a respective odd number of storage elements under test.
5 . The method of claim 1 , comprising, prior to said generating a plurality of parity protect groups generating a protect list comprising all storage elements of the electronic device less at least a set of storage elements for which inclusion in a parity protect group is not desired.
6 . The method of claim 1 , wherein said plurality of parity protect groups are associated with a same clock domain.
7 . The method of claim 6 , comprising, prior to said generating a plurality of parity protect groups, identifying a respective set of control signal inputs for at least each storage element in the same clock domain that is to be included in a parity protect group.
8 . The method of claim 1 , comprising, prior to said generating a plurality of parity protect groups:
determining a maximum number of storage elements under test for each of the plurality of parity protect groups; and
generating a super parity protect group having more than the determined maximum number of storage elements, and associated with the same set of control signal inputs,
wherein said generating a plurality of parity protect groups comprises parsing said super parity protect group into the plurality of protect groups, each of which comprising no more than the determined maximum number of storage elements under test.
9 . The method of claim 1 , wherein said generating a plurality of parity protect groups comprises selecting storage elements for the plurality of parity protect groups based, at least in part, on a storage element timing constraint.
10 . The method of claim 9 , wherein said storage element timing constraint comprises at least one of: storage element setup margin and/or storage element clock-to-out margin.
11 . The method of claim 9 , wherein said generating a plurality of parity protect groups comprises excluding from the plurality of parity protect groups storage elements having respective timing constraints that are less than a threshold timing constraint.
12 . The method of claim 9 , wherein said generating a plurality of parity protect groups comprises:
determining a target percentage of storage elements in a circuit design to parity check to reach a desired level of reliability; and
identifying the target percentage of storage elements in the circuit design generally having the loosest timing constraints for inclusion in the parity protect groups.
13 . A method of producing an electronic device with on-board error detection, the method comprising:
generating a plurality of parity protect groups, where each of the plurality of parity protect groups comprises:
a number of storage elements under test, each of which is coupled to a same set of control signal inputs;
a parity test storage element coupled to said same set of control signal inputs; and
a parity test output;
generating a report point comprising a report point storage element that outputs parity test results; and
fabricating the electronic device comprising said plurality of parity protect groups and said report point,
wherein said generating a plurality of parity protect groups comprises selecting storage elements for the plurality of parity protect groups based, at least in part, on a storage element timing constraint.
14 . The method of claim 13 , wherein said storage element timing constraint comprises at least one of: storage element setup margin and/or storage element clock-to-out margin.
15 . The method of claim 13 , wherein said selecting storage elements for the plurality of parity protect groups comprises:
including in the plurality of parity protect groups a first set of storage elements having acceptably sized respective timing constraints; and
excluding from the plurality of parity protect groups a second set of storage elements having unacceptably sized respective timing constraints.
16 . The method of claim 13 , wherein said selecting storage elements for the plurality of parity protect groups comprises:
determining a target percentage of storage elements in a circuit design to parity check; and
identifying the target percentage of storage elements in the circuit design generally having the loosest timing constraints for inclusion in the parity protect groups.
17 . A method of producing an electronic device with on-board error detection, the method comprising:
generating a plurality of parity protect groups, where each of the plurality of parity protect groups comprises:
a number of storage elements under test, each of which is coupled to a same set of control signal inputs comprising a same clock net;
a parity test storage element coupled to at least a portion of said same set of control signal inputs; and
a parity test output;
generating a report point comprising a report point storage element that outputs parity test results;
logically combining each of the respective parity test outputs of each of the plurality of parity protect groups at an input of the report point storage element; and
fabricating the electronic device comprising said plurality of parity protect groups and said report point,
wherein the plurality of parity protect groups are all associated with said same set of control signal inputs.
18 . The method of claim 17 , wherein the same set of control signal inputs comprises the same clock net, a same clear net, and a same preset net.
19 . The method of claim 18 , wherein for each of the plurality of parity protect groups, the number of storage elements under test is an odd number.
20 . The method of claim 18 , wherein for each of the plurality of parity protect groups that have an even number of storage elements:
a clear input of the parity test storage element is connected to a logical OR of the same clear net and the same preset net; and
a preset input of the parity test storage element is connected to a logical 0.