IP Library Granted Patent US 8,780,912
Granted Patent B2
US 8,780,912 · App. 13/015,940 · Granted Jul 15, 2014

Systems and method for routing data

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Quick Facts
Patent No.
US 8,780,912
App. No.
13/015,940
Granted
Jul 15, 2014
Kind
B2
Abstract

A system and method for routing frames to one or more loops is provided. The system includes a processor operable to receive a frame and a storage device operable to store instructions. The instructions may enable the processor to forward the frame according to an address field of the frame. The processor may forward the frame to a first loop if the address field of the frame is associated with the first loop. The processor may forward the frame to a second loop if the address field of the frame is associated with the second loop. The processor may also reject and discard the frame based on the address field of the frame.

Claims (46)

1. A system for routing frames to one of a first loop and a second loop, the system comprising:

a first processor;

a first storage device connected to the first processor; and

a plurality of instructions stored on the first storage device, the plurality of instructions operable to:

enable the first processor to receive a frame,

cause a mask be to applied to an address field of the frame to produce a filtered address field of the frame,

cause the frame to be forwarded to the first loop if the filtered address field of the frame is associated with the first loop, wherein the address field includes a priority indication,

cause the frame to be forwarded to the second loop if the filtered address field of the frame is associated with the second loop,

cause the frame to be removed if the filtered address field of the frame is not associated with one of the first loop and the second loop, and

cause a plurality of filtered address fields to be probed if a second storage device is connected to one of the first loop and the second loop.

2. The system of claim 1 , further comprising:

a plurality of ports; and

a first control module coupled to the plurality of ports.

3. The system of claim 1 , further comprising:

a first port;

a second port;

a first control module coupled to the first port; and

a second control module coupled to the second port.

4. The system of claim 1 , wherein the frame is routed according to a predefined rule.

5. The system of claim 1 , wherein the frame is removed according to predefined rule.

6. The system of claim 1 , wherein one or more frames are grouped according to priority.

7. The system of claim 1 , wherein the first processor is operably connected to a DMA control module.

8. A system for routing data to one of a plurality of paths, the system comprising:

a receiver operable to receive the data; and

a processor operable to apply a mask to a priority indication associated with the data to produce a filtered address field that is used to determine a route according to one or more rules;

wherein if a storage device is connected to any path in the plurality of paths, a probe is sent to a plurality of filtered address fields,

wherein if the priority indication is associated with a particular path in the plurality of paths, the route comprises the particular path, and

wherein if the priority indication is associated with none of the paths in the plurality of paths, the data is rejected.

9. The system of claim 8 , wherein the data is a frame.

10. The system of claim 8 , wherein the plurality of paths comprises loops.

11. The system of claim 8 , wherein the data is routed according to a predefined rule.

12. The system of claim 8 , wherein the data is rejected according to predefined rule.

13. The system of claim 8 , wherein the data is grouped according to priority.

14. The system of claim 8 , wherein the processor is operably connected to a DMA control module.

15. A method for routing data to one of a plurality of paths, the method comprising:

receiving the data;

applying a mask to a priority indication associated with the data to produce a filtered priority indication associated with the data;

checking the filtered priority indication data;

routing the data if the filtered priority indication is associated with one or more particular paths in the plurality of paths;

probing a plurality of filtered priority indications if a storage device is connected to any path in the plurality of paths; and

discarding the data if the priority indication is associated with none of the paths in the plurality of paths.

16. The method of claim 15 , wherein the data is a frame.

17. The method of claim 15 , wherein the plurality of paths comprises loops.

18. The method of claim 15 , wherein the particular path is associated with a particular priority indication according to a rule.

19. The method of claim 15 , wherein an address field of the data comprises the priority indication.

20. The method of claim 15 , wherein the data is grouped according to priority.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: EMULEX CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036942/0213 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2014
From: EMULEX DESIGN AND MANUFACTURING CORPORATION
To: EMULEX CORPORATION
Reel/Frame 032087/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2011
From: BERMAN, STUART B.
To: EMULEX DESIGN & MANUFACTURING CORPORATION
Reel/Frame 026482/0477 →