Method and interface for access to memory within a first electronic device by a second electronic device
View Patent ↗In one embodiment of the present invention, a two-register interface is provided by a first electronic device to allow access to memory within the electronic device by external electronic devices. The two-register interface is mapped from the memory of an accessing, second electronic device. READ and WRITE accesses are transmitted from the accessing, second electronic device to the two-register interface through a communications medium. A first register of the two-register interface directs access to a particular memory location, and the second register of the two-register interface provides a portal for both READ and WRITE access to the particular memory location.
1. An interface to the memory of a first electronic device that allows a second electronic device to access the memory of the first electronic device, the interface comprising:
a first register, provided by the first electronic device, into which the second electronic device enters an indication of a memory location within the first electronic device;
a second register, provided by the first electronic device, from which the second electronic device reads a data value currently stored in the memory location within the first electronic device and into which the second electronic device writes a data value that is stored into the memory location; and
signal lines and state-machine logic that reads data value currently stored in the memory location within the first electronic device into the second register and that writes a data value written to the second register into the memory location.
2. The interface of claim 1 wherein the first register and the second register are mapped from a memory within the second electronic device through a communications medium.
3. The interface of claim 2 wherein the communications medium is a PCIe serial connection.
4. The interface of claim 3 wherein the PCIe serial connection supports multiple PCI functions, and each PCIe function is associated with a discrete interface comprising first and second registers.
5. The interface of claim 1 wherein the first electronic device includes a CPU that also accesses the memory within the first electronic device.
6. The interface of claim 5 wherein the signal lines and state-machine logic that reads data value currently stored in the memory location within the first electronic device into the second register and that writes a data value written to the second register into the memory location further comprise:
a first multiplexing switch connected, on a back side, via signal lines to the interface and to the CPU, and connected, on a front side, via signal lines to the memory within the first electronic device, the first multiplexing switch including an address decoder shared by the interface and CPU and a state-machine implemented multiplexer.
7. The interface of claim 6 wherein the first electronic device is connected to a multiple-function communications medium, each function associated with a discrete two-register interface, and wherein a second multiplexing switch arbitrates among the discrete two-register-interfaces and is connected to the first multiplexing switch.
8. The interface of claim 1 wherein the indication of a memory location is an address of the memory location.
9. A method for providing access to a memory of a first electronic device to a second electronic device, the method comprising:
providing a first register and a second register in the first electronic device;
when the second electronic device enters an indication of a memory location within the first electronic device into the first register, establishing an association between the second register and the memory location;
when the second electronic device reads a data value from the second register, providing to the second electronic device with a data value currently stored in the memory location; and
when the second electronic device writes a data value into the second register, storing the data value into the memory location.
10. The method of claim 9 further comprising mapping the first and second register to the memory of second electronic device via a communications medium.
11. The method of claim 10 wherein the communications medium is a PCIe serial connection.
12. An interface to the memory of an intermediate electronic device, such as an I/O controller, that allows a host device to access the memory of the intermediate electronic device, the interface comprising:
a first register, provided by the intermediate device, into which the host device enters an indication of a memory location within the intermediate device;
a second register, provided by the intermediate device, from which the host device reads a data value currently stored in the memory location within the intermediate device and into which the host device writes a data value that is stored into the memory location; and
signal lines and state-machine logic that reads data value currently stored in the memory location within the intermediate device into the second register and that writes a data value written to the second register into the memory location.
13. The interface of claim 12 wherein the first register and the second register are mapped from a memory within the host device through a communications medium.
14. The interface of claim 13 wherein the communications medium is a PCIe serial connection.
15. The interface of claim 14 wherein the PCIe serial connection supports multiple PCI functions, and each PCIe function is associated with a discrete interface comprising first and second registers.
16. The interface of claim 12 wherein the intermediate device includes a CPU that also accesses the memory within the intermediate device.
17. The interface of claim 16 wherein the signal lines and state-machine logic that reads data value currently stored in the memory location within the intermediate device into the second register and that writes a data value written to the second register into the memory location further comprise:
a first multiplexing switch connected, on a back side, via signal lines to the interface and to the CPU, and connected, on a front side, via signal lines to the memory within the intermediate device, the first multiplexing switch including an address decoder shared by the interface and CPU and a state-machine implemented multiplexer.
18. The interface of claim 17 wherein the intermediate device is connected to a multiple-function communications medium, each function associated with a discrete two-register interface, and wherein a second multiplexing switch arbitrates among the discrete two-register-interfaces and is connected to the first multiplexing switch.
19. The interface of claim 12 wherein the indication of a memory location is an address of the memory location.