System and Method for Debugging
A system and method for debugging an ASIC are described herein. In accordance with this disclosure, a trigger logic unit may trigger a transfer of a multi-bit signal from an internal ASIC state to a compression engine. The compression engine may compress the multi-bit signal to create a compressed signal. A packet engine may packetize the compressed signal for transmission via a debug interface.
1 . A system operable to enable debugging, comprising:
a trigger logic unit operable to trigger a transfer of a multi-bit signal from an internal ASIC state to a packet engine; and
the packet engine operable to packetize the multi-bit signal into one or more output packets for transmission via a debug interface, wherein the packet engine is operable to add one or both of a timestamp and a packet sequence number to the one or more output packets.
2 . The system of claim 1 , wherein the system comprises a compression engine operable to compress the multi-bit signal.
3 . The system of claim 2 , wherein the compression engine comprises a history buffer for the storage of a previous multi-bit signal.
4 . The system of claim 2 , wherein the system comprises a Ping-Pong FIFO buffer operable to transfer packets between the compression engine and the packet engine.
5 . The system of claim 1 , wherein the internal ASIC state is accessible via a hardware debug ring.
6 . The system of claim 1 , wherein the debug interface comprises a MAC layer processor.
7 . The system of claim 1 , wherein the debug interface comprises a physical coding sub-layer.
8 . The system of claim 1 , wherein the debug interface comprises a SERDES.
9 . The system of claim 1 , wherein the debug interface is coupled to a transmit path port.
10 . The system of claim 1 , wherein the packet engine is operable to prepend a programmable header.
11 . The system of claim 10 , wherein the programmable header comprises a trigger location.
12 . The system of claim 1 , wherein the trigger logic unit comprises a pointer generator operable to generate a control signal for the transfer of the multi-bit signal.
13 . A method for debugging, comprising:
transferring a multi-bit signal from an internal ASIC state;
generating a timestamp and a packet sequence number;
packetizing the multi-bit signal, the timestamp and the packet sequence number, thereby generating one or more output packets; and
transmitting the one or more output packets via a debug interface.
14 . The method of claim 13 , wherein the internal ASIC state is accessible via a hardware debug ring.
15 . The method of claim 13 , wherein the method comprises compressing the multi-bit signal according to a previous multi-bit signal.
16 . The method of claim 13 , wherein the method comprises transferring the multi-bit signal via a Ping-Pong FIFO buffer.
17 . The method of claim 13 , wherein the debug interface comprises a MAC layer processor.
18 . The method of claim 13 , wherein the method comprises receiving debug command packets and triggering the transfer of the multi-bit signal from the internal ASIC state according to the receive debug command packets.
19 . The method of claim 13 , wherein the debug interface is coupled to a transmit path port.
20 . The method of claim 13 , wherein triggering a transfer of the multi-bit signal comprises generating a control signal.