IP Library Granted Patent US 7,979,592
Granted Patent B1
US 7,979,592 · App. 12/028,801 · Granted Jul 12, 2011

Virtualization bridge device

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Quick Facts
Patent No.
US 7,979,592
App. No.
12/028,801
Granted
Jul 12, 2011
Kind
B1
Abstract

A computer system includes a shared I/O device including functions providing access to device local memory space, and a plurality of roots coupled to the shared I/O device via a switch fabric. A first root assigns a first address in a first root memory space to a first function. A second root assigns a second address in a second root memory space to a second function. The switch fabric maps the first root memory space to a first portion of device local memory space and the second root memory space to a second portion of device local memory space. Subsequently, the switch receives a data transaction request from the first root targeted to the first address, translates the first address to a corresponding location in the first portion of the device local memory space based on the mapping, and routes the data transaction request to the I/O device.

Claims (66)

1. A method for use in a PCI Express system comprising a plurality of independent PCI Express roots coupled to a shared single-root input/output virtualization (SR-IOV) endpoint via a bridge device, the method comprising:

a first root of the plurality of independent PCI Express roots independently assigning a first address in a first root local memory space to a first virtual function of the SR-IOV endpoint, wherein the first root corresponds to a first virtual hierarchy (VH) in the PCI Express system, and a second root of the plurality of independent PCI Express roots assigning a second address in a second root local memory space to a second virtual function of the SR-IOV endpoint, wherein the second root corresponds to a second VH in the PCI Express system that is different from the first VH;

mapping in the bridge device the first root local memory space to a first portion of the SR-IOV endpoint local memory space, and mapping the second root local memory space to a second portion of the SR-IOV endpoint local memory space, whereby both the first root local memory space and the second root local memory space are concurrently mapped to the SR-IOV endpoint local memory space;

performing in the bridge device:

receiving a first request from the first root without an identification of which of said roots is a source of the first request, the first request comprising a first target address;

receiving a second request from the second root without an identification of which of said roots is a source of the second request, the second request comprising a second target address;

identifying a source of the first request based at least in part on a port via which the first request was received;

identifying a source of the second request based at least in part on a port via which the second request was received;

determining a target of each of the first request and the second request based at least in part on an identification of a source of the first request and the second request, respectively; and

conveying both of the first request and the second request to the SR-IOV endpoint with an identification of which of said plurality of independent PCI Express roots is a source of the first request and the second request, respectively.

2. The method of claim 1 , further comprising:

translating the first target address to a first translated address in a first address space; and

translating the second address to a second translated address in a second address space, the second address space being different from the first address space;

wherein the first request conveyed to the SR-IOV endpoint includes the first translated address, and wherein the second request conveyed to the SR-IOV endpoint includes the second translated address.

3. The method of claim 2 , wherein the first target address and the second target address are the same.

4. The method of claim 2 , wherein the first request corresponds to a first virtual function in the SR-IOV endpoint, and the second request corresponds to a second virtual function in the SR-IOV endpoint.

5. The method of claim 4 , wherein the first virtual function and the second virtual function both correspond to a same physical function in the SR-IOV endpoint.

6. The method of claim 1 , wherein the identification of a source of the first request and the second request is based at least in part on a port via which a given root is coupled to the bridge device.

7. The method of claim 1 , wherein the first request includes a requester ID (RID) that does not identify a specific virtual hierarchy (VH), and wherein the method further comprises:

the bridge device modifying the requester ID to a VH identifier (VH ID) that identifies a specific VH to which the first request corresponds; and

conveying the first request to the shared SR-IOV endpoint with the VH ID and without the RID.

8. A computer system comprising:

a shared single-root input/output virtualization (SR-IOV) endpoint;

a plurality of independent PCI Express roots coupled to the shared SR-IOV endpoint via a bridge device utilizing a PCI Express protocol;

wherein a first root of the plurality of independent PCI Express roots is configured to independently assign a first address in a first root local memory space to a first virtual function of the SR-IOV endpoint, wherein the first root corresponds to a first virtual hierarchy (VH) in the PCI Express system and a second root of the plurality of independent PCI Express roots is configured to independently assign a second address in a second root local memory space to a second virtual function of the SR-IOV endpoint, wherein the second root corresponds to a second VH in the PCI Express system that is different from the first VH;

wherein the bridge device is configured to:

map the first root local memory space to a first portion of the SR-IOV endpoint local memory space, and map the second root local memory space to a second portion of the SR-IOV endpoint local memory space, whereby both the first root local memory space and the second root local memory space are concurrently mapped to the SR-IOV endpoint local memory space;

receive a first request from a first root of the plurality of roots without an identification of which of said plurality of independent roots is a source of the first request, the first request comprising a first target address;

receive a second request from a second root of the plurality of roots without an identification of which of said plurality of independent roots is a source of the second request, the second request comprising a second target address;

identify a source of the first request based at least in part on a port via which the first request was received;

identify a source of the second request based at least in part on a port via which the second request was received;

determine a target of each of the first request and the second request based at least in part on an identification of a source of the first request and the second request, respectively;

convey both of the first request and the second request to the SR-IOV endpoint with an identification of which of said plurality of independent PCI Express roots is a source of the first request and the second request, respectively.

9. The system of claim 8 , wherein the bridge device is further configured to:

translate the first target address to a first translated address in a first address space; and

translate the second address to a second translated address in a second address space, the second address space being different from the first address space;

wherein the first request conveyed to the SR-IOV endpoint includes the first translated address, and wherein the second request conveyed to the SR-IOV endpoint includes the second translated address.

10. The system of claim 9 , wherein the first and the second target addresses are the same.

11. The system of claim 9 , wherein the first request corresponds to a first virtual function in the SR-IOV endpoint, and the second request corresponds to a second virtual function in the SR-IOV endpoint.

12. The system of claim 11 , wherein the first virtual function and the second virtual function both correspond to a same physical function in the SR-IOV endpoint.

13. The system of claim 8 , wherein the identification of a source of the first request and the second request is based at least in part on a port via which a given root is coupled to the bridge device.

14. The system of claim 8 , wherein the first request includes a requester ID (RID) that does not identify a specific virtual hierarchy (VH), and wherein the bridge device is further configured to:

modify the requester ID to a VH identifier (VH ID) that identifies a specific VH to which the first request corresponds; and

convey the first request to the shared SR-IOV endpoint with the VH ID and without the RID.

15. A bridge device for coupling a shared single-root input/output virtualization (SR-IOV) endpoint to a plurality of independent PCI Express roots, wherein a first root of the plurality of independent PCI Express roots independently assigns a first address in a first root local memory space to a first virtual function of the SR-IOV endpoint, and a second root of the plurality of independent PCI Express roots assigns a second address in a second root local memory space to a second virtual function of the SR-IOV endpoint, where the bridge device is configured to:

map the first root local memory space to a first portion of the SR-IOV endpoint local memory space, and map the second root local memory space to a second portion of SR-IOV endpoint local memory space, whereby both the first root local memory space and the second root local memory space are concurrently mapped to the SR-IOV endpoint local memory space, and wherein the first root corresponds to a first virtual hierarchy (VH) in the PCI Express system and the second root corresponds to a second VH in the PCI Express system that is different from the first VH;

receive a first request from a first root of the plurality of roots without an identification of which of said plurality of independent roots is a source of the first request, the first request comprising a first target address;

receive a second request from a second root of the plurality of roots without an identification of which of said plurality of independent roots is a source of the second request, the second request comprising a second target address;

identify a source of the first request based at least in part on a port via which the first request was received;

identify a source of the second request based at least in part on a port via which the second request was received;

determine a target of each of the first request and the second request based at least in part on an identification of a source of the first request and the second request, respectively;

convey both of the first request and the second request to the SR-IOV endpoint with an identification of which of said plurality of independent PCI Express roots is a source of the first request and the second request, respectively.

16. The bridge device of claim 15 , wherein the bridge device is further configured to:

translate the first target address to a first translated address in a first address space; and

translate the second address to a second translated address in a second address space, the second address space being different from the first address space;

wherein the first request conveyed to the SR-IOV endpoint includes the first translated address, and wherein the second request conveyed to the SR-IOV endpoint includes the second translated address.

17. The bridge device of claim 16 , wherein the first and the second target addresses are the same.

18. The bridge device of claim 16 , wherein the first request corresponds to a first virtual function in the SR-IOV endpoint, and the second request corresponds to a second virtual function in the SR-IOV endpoint.

19. The bridge device of claim 18 , wherein the first virtual function and the second virtual function both correspond to a same physical function in the SR-IOV endpoint.

20. The bridge device of claim 15 , wherein the identification of a source of the first request and the second request is based at least in part on a port via which a given root is coupled to the bridge device.

21. The bridge device of claim 15 , wherein the first request includes a requester ID (RID) that does not identify a specific virtual hierarchy (VH), and wherein the bridge device is further configured to:

modify the requester ID to a VH identifier (VH ID) that identifies a specific VH to which the first request corresponds; and

convey the first request to the shared SR-IOV endpoint with the VH ID and without the RID.

22. The method of claim 1 , wherein identifying said source of the first request comprises identifying a root that is the source of the first request, and wherein identifying said source of the second request comprises identifying a root that is the source of the second request.

23. The system of claim 22 , wherein the first request and the second request received by the SR-IOV endpoint are received in respective packets which do not include a field for a identifying a source of the respective packets, and wherein the identification of which of said roots is a source of the respective packets is encoded in a field designated for other purposes.

24. The bridge device of claim 15 , wherein identifying said source of the first request comprises identifying a root that is the source of the first request, and wherein identifying said source of the second request comprises identifying a root that is the source of the second request.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: EMULEX CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036942/0213 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2014
From: EMULEX DESIGN AND MANUFACTURING CORPORATION
To: EMULEX CORPORATION
Reel/Frame 032087/0842 →