Data bus efficiency via cache line usurpation
View Patent ↗Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
1. A method for allocating cache memory to increase processor efficiency, comprising:
identifying a main memory location to be accessed in a main memory;
determining whether the main memory location is already associated with a cache memory in a processor, the processor configured for accessing the main memory through bus transactions;
allocating a cache memory location if the main memory location is not already associated with the cache memory;
determining whether information at the main memory location is required for a future computation by the processor; and
bypassing a reading of data from the main memory location to the cache memory location if the information at the main memory location is not required for a future computation by the processor; and
initializing the allocated cache memory location while bypassing the reading of data from the main memory location to the cache memory location.
2. The method of claim 1 , further comprising setting an initialization pattern through a processor to a desired pattern.
3. The method of claim 1 , further comprising initializing the cache memory location if the main memory location is already associated with cache memory.
4. The method of claim 1 , further comprising specifying a number of cache lines to allocate so that the number of cache lines are allocated with a single request.
5. The method of claim 4 , further comprising:
initializing the cache memory location through hardware to eliminate a need to initialize the cache memory location through software.
6. The method of claim 1 , further comprising initializing the allocated cache memory location through hardware to eliminate a need to initialize the cache memory location through software.
7. The method of claim 6 , wherein the initialization sets a value of the cache memory location to zero.
8. A computer processor with an efficient cache memory allocation, comprising:
a cache memory within the computer processor;
a connection to a main memory external to the computer processor; and
a control unit coupled to the cache memory, wherein the control unit is operable to:
control the cache memory and identify a main memory location to be accessed in the main memory,
determine whether the main memory location is already associated with the cache memory,
allocate a cache memory location if the main memory location is not already associated with the cache memory,
determine whether information at the main memory location is required for a future computation by the processor; and
bypass reading data from the main memory location to the cache memory location if the information at the main memory location is not required for a future computation by the processor; and
initialize the allocated cache memory location while bypassing the reading of data from the main memory location to the cache memory location.
9. The computer processor of claim 8 , the control unit further programmed for initializing the cache memory location through hardware to eliminate a need to initialize the cache memory location through software.
10. The computer processor of claim 8 , the control unit further programmed for initializing the cache memory location if the main memory location is already associated with cache memory.
11. The computer processor of claim 8 , wherein the computer processor is included in a storage area network.
12. The computer processor of claim 8 , wherein the computer processor is included in an Ethernet network.
13. The computer processor of claim 8 , wherein the computer processor is included in a network system.
14. The computer processor of claim 8 , the control unit further programmed for specifying a number of cache lines to allocate so that the number of cache lines are allocated with a single request.
15. The method of claim 14 , the control unit further programmed for initializing the cache memory location through hardware to eliminate a need to initialize the cache memory location through software.
16. A computer-readable storage medium comprising program code for efficiently allocating a cache memory location, the program code for causing performance of a method comprising:
identifying a main memory location to be accessed in a main memory,
determining whether the main memory location is already associated with a cache memory,
allocating a cache memory location if the main memory location is not already associated with the cache memory,
determining whether information at the main memory location is required for a future computation by the processor,
bypassing a reading of data from the main memory location to the cache memory location if the information at the main memory location is not required for a future computation by the processor, and
initializing the allocated cache memory location while bypassing the reading of data from the main memory location to the cache memory location.
17. The computer-readable storage medium of claim 16 , the program code further for causing performance of a method comprising initializing the cache memory location if the main memory location is already associated with cache memory.