IP Library Granted Patent US 7,917,658
Granted Patent B2
US 7,917,658 · App. 12/126,891 · Granted Mar 29, 2011

Switching apparatus and method for link initialization in a shared I/O environment

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Quick Facts
Patent No.
US 7,917,658
App. No.
12/126,891
Granted
Mar 29, 2011
Kind
B2
Abstract

An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains. The link is initialized in a manner that is transparent to the plurality of operating system domains.

Claims (20)

1. A shared I/O apparatus, comprising:

a shared I/O endpoint, configured to request/complete transactions for each of a plurality of operating system domains, wherein said each of a plurality of operating system domains communicate with said shared I/O endpoint according to a protocol that provides for routing of transactions only for a single operating system domain, said shared I/O endpoint comprising:

a first I/O port, coupled to a link, configured to request/complete said transactions for each of said plurality of operating system domains according to a variant of said protocol, wherein said variant comprises encapsulating an OS domain header within a transaction layer packet that otherwise comports with said protocol, and wherein a particular OS domain header associates a particular transaction layer packet with a particular one of said plurality of operating system domains; and

link training logic, coupled to said first I/O port, configured to initialize said link, wherein said link is initialized in a manner that is transparent to said plurality of operating system domains.

2. The shared I/O apparatus as recited in claim 1 , wherein said link training logic employs a mechanism according to said protocol to initialize said link, and wherein said mechanism would otherwise be ignored by a non-shared input/output endpoint, and wherein said shared input/output endpoint recognizes said mechanism.

3. The shared I/O apparatus as recited in claim 2 , wherein the shared input/output endpoint provides a count indicating a number of said plurality of operating system domains that said shared input/output endpoint is capable of supporting.

4. The shared I/O apparatus as recited in claim 2 , wherein said protocol comprises the PCI Express protocol, and wherein said mechanism comprises a PCI Express data link layer packet that is undefined.

5. The shared I/O apparatus as recited in claim 1 , wherein said shared input/output endpoint is configured to associate each of said transactions with a corresponding one of said plurality of operating system domains (OSDs), said corresponding one of said plurality of OSDs corresponding to one or more root complexes.

6. The shared I/O apparatus as recited in claim 1 , wherein said link is initialized without any intervention by system software.

7. The shared I/O apparatus as recited in claim 6 , wherein said system software comprises operating systems, basic input/output systems (BIOS), configuration applications, and management applications.

8. A root complex apparatus, comprising:

a root complex, wherein said root complex corresponds to a plurality of operating system domains, and wherein each of said plurality of operating system domains communicate with a shared I/O endpoint according to a protocol that provides for routing of transactions only for a single operating system domain, said root complex comprising:

a first I/O port, coupled to a link, configured to request/complete said transactions for each of said plurality of operating system domains according to a variant of said protocol, wherein said variant comprises encapsulating an OS domain header within a transaction layer packet that otherwise comports with said protocol, and wherein a particular OS domain header associates a particular transaction layer packet with a particular one of said plurality of operating system domains; and

link training logic, coupled to said first I/O port, configured to initialize said link, wherein said link is initialized in a manner that is transparent to said plurality of operating system domains.

9. The root complex apparatus as recited in claim 8 , wherein said link training logic employs a mechanism according to said protocol to initialize said link, and wherein said mechanism would otherwise be ignored by a second root complex that corresponds to a single operating system domain, and wherein said root complex recognizes said mechanism.

10. The root complex apparatus as recited in claim 9 , wherein said root complex provides a count indicating a number of the plurality of operating system domains that said root complex is capable of supporting.

11. The root complex apparatus as recited in claim 9 , wherein said protocol comprises the PCI Express protocol, and wherein said mechanism comprises a PCI Express data link layer packet that is undefined.

12. The root complex apparatus as recited in claim 8 , wherein said root complex is configured to associate each of said transactions with a corresponding one of said plurality of operating system domains (OSDs).

13. The root complex apparatus as recited in claim 8 , wherein said link is initialized without any intervention by system software.

14. The root complex apparatus as recited in claim 13 , wherein said system software comprises operating systems, basic input/output systems (BIOS), configuration applications, and management applications.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: EMULEX CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036942/0213 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2014
From: EMULEX DESIGN AND MANUFACTURING CORPORATION
To: EMULEX CORPORATION
Reel/Frame 032087/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2010
From: NEXTIO INC.
To: EMULEX DESIGN AND MANUFACTURING CORPORATION
Reel/Frame 024434/0248 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2008
From: PETTEY, CHRISTOPHER J.; KHAN, ASIF; PAGAN, ANNETTE; PEKKALA, RICHARD E.; UTLEY, ROBERT HASKELL
To: NEXTIO INC.
Reel/Frame 020997/0884 →