IP Library Granted Patent US 7,020,716
Granted Patent B2
US 7,020,716 · App. 09/944,716 · Granted Mar 28, 2006

Method and system for verifying the hardware implementation of TCP/IP

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Quick Facts
Patent No.
US 7,020,716
App. No.
09/944,716
Granted
Mar 28, 2006
Kind
B2
Abstract

The present invention provides for a method and system for verifying hardware operation of an Application Specific Integrated Circuit (“ASIC”) chip. The ASIC includes microcode logic for enabling Transmission Control Protocol/Internet Protocol (“TCP/IP”) processing. The method is performed in a system that includes a first computing device having a processor and computer code for simulating a computing device that includes the ASIC. Wherein the ASIC is tested against a conventional TCP/IP stack included in a second computing device coupled to the first computing device.

Claims (16)

1. A method for verifying the hardware operation of an Application Specific Integrated Circuit (“ASIC”) chip having microcode logic for enabling Transmission Control Protocol/Internet Protocol (“TCP/IP”) processing, said method performed in a system that comprises a first computing device having a processor and register transfer level (RTL) code for simulating a computing device that includes said ASIC, said system further comprising a second computing device coupled to said first computing device via a network, said second computing device comprising a processor and a TCP/IP stack for performing TCP/IP processing, said method comprising the steps of:

(a) causing said RTL code to initiate a TCP/IP connection between said first computing device and said second computing device over said network, including the generation of a SYN packet addressed to said second computing device that is coupled by said first computing device to said network so as to enable said SYN packet to be received and processed by said second computing device;

(b) detecting by said first computing device a SYN-ACK packet generated by said second computing device in response to its receipt of said SYN packet; and

(c) causing said RTL code to process said SYN-ACK packet and to generate an ACK packet that is coupled by said first computing device to said network for receipt by said second computing device, so as to complete said RTL code initiated TCP/IP connection, whereby a first TCP/IP timer is deliberately slowed relative to a second TCP/IP timer that would have been employed if said RTL code is not employed to generate said ACK packet, said first TCP/IP timer being slowed in order to prevent said second computing device from retransmitting said SYN-ACK packet due to a time-out event.

2. The method of claim 1 further comprising the steps of:

(d) causing said first computing device to detect on said network a SYN packet addressed to said RTL code, thereby recognizing that said second computing device has initiated a TCP/IP connection between said first computing device and said second computing device over said network, and for coupling said SYN packet to said RTL code;

(e) processing said SYN packet by said RTL code, and causing said RTL code to generate a SYN-ACK packet that is coupled by said first computing device to the network so as to enable said SYN-ACK packet to be received by said second computing device; and

(f) detecting by said first computing device an ACK packet generated by said second computing device in response to its receipt of said SYN-ACK packet, so as to complete said second computing device initiated TCP/IP connection.

3. The method of claim 1 wherein said RTL initiated TCP/IP connection enables the transfer of at least one packet of data between said first computing device and said second computing device.

4. A system for verifying the hardware operation of an Application Specific Integrated Circuit (“ASIC”) chip having microcode logic for enabling Transmission Control Protocol/Internet Protocol (“TCP/IP”) processing, said system comprising:

a first computing device having a processor and register transfer level (RTL) code for simulating a computing device that includes said ASIC; and

a second computing device coupled to said first computing device via a network, said second computing device comprising a processor and a TCP/IP stack for performing TCP/IP processing, wherein: said RTL code is designed to initiate a TCP/IP connection between said first computing device and said second computing device over said network, including the generation of a SYN packet addressed to said second computing device that is coupled by said first computing device to said network so as to enable said SYN packet to be received and processed by said second computing device; said first computing device is operative to detect a SYN-ACK packet generated by said second computing device in response to its receipt of said SYN packet; and said RTL code is designed to process said SYN-ACK packet and to generate an ACK packet that is coupled by said first computing device to said network for receipt by said second computing device, so as to complete said RTL code initiated TCP/IP connection, whereby a first TCP/IP timer is deliberately slowed relative to a second TCP/IP timer that would have been employed if said RTL code is not employed to generate said ACK packet, said first TCP/IP timer being slowed in order to prevent said second computing device from retransmitting said SYN-ACK packet due to a time-out event.

5. The system of claim 4 , wherein: said first computing device is further operative to detect on said network a SYN packet addressed to said RTL code, thereby recognizing that said second computing device has initiated a TCP/IP connection between said first computing device and said second computing device over said network, and for coupling said SYN packet to said RTL code; said RTL code is further designed to process said SYN packet to generate a SYN-ACK packet that is coupled by said first computing device to the network so as to enable said SYN-ACK packet to be received by said second computing device; and said first computing device is further operative to detect an ACK packet generated by said second computing device in response to its receipt of said SYN-ACK packet, so as to complete said second computing device initiated TCP/IP connection.

6. The system of claim 4 wherein said first computing device and said second computing device are connected via one or more Local Area Networks.

7. The system of claim 4 wherein said RTL code is Verilog code.

8. The system of claim 4 wherein said first computing device is a Sun workstation and said second computing device is a Linux machine, and said system further comprised a third computing device that is a Linux machine, said third computing device coupled between said first and second computing devices, wherein said third computing device is operative to receive at least one packet from said first computing device addressed from said RTL code to said second computing device and to place each said packet on the network, said third computing device is further operative to look for at least one packet from said second computing device addressed to said RTL code and to forward each said packet to said first computing device.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: EMULEX CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036942/0213 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2014
From: EMULEX DESIGN AND MANUFACTURING CORPORATION
To: EMULEX CORPORATION
Reel/Frame 032087/0842 →