Cache pollution avoidance

1. A method for operating a cache memory, comprising:

defining a type of data as short life data according to an expected operation of particular software, wherein the short life data is data that is anticipated to be used by the processor only for a short amount of time;

defining a short life portion in the cache memory;

determining whether a data block to be cached is a short life data block; and

in the event that the data block to be cached is a short life data block, storing the data block to be cached only in the short life portion of the cache memory so that useful data in other portions of the cache memory is not to be replaced by the short life data, the short life portion being a portion of the cache memory that does not encompass the entire cache memory.

2. The method of claim 1 , wherein determining whether a data block to be cached is a short life data block includes determining whether all data in the data block to be cached is short life data.

3. The method of claim 1 , wherein the short life portion of the cache memory is less than one quarter of the total size of the cache memory.

4. The method of claim 1 , wherein the method is performed without modifying a standard cache controller.

5. The method of claim 1 further, including:

receiving an actual memory address of a data item to be cached that is part of the data block to be cached;

translating the actual address to a virtual address, the virtual address being associated by a cache controller with an area of the cache that is the same as or part of the short life portion of the cache;

instructing a processor to access memory at the virtual address;

sending a memory access command based on the virtual address by the processor to the memory;

interrupting the memory access command before it reaches the memory;

removing the virtual address from the memory access command and replacing it with the actual address; and

sending the access command to the memory.

6. The method of claim 5 , wherein the instructing a processor to access memory at the virtual address causes a cache controller to store the accessed memory in the short life portion of the cache based on the virtual address.

7. The method of claim 1 wherein the short life data comprises network communications data.

8. The method of claim 7 wherein the short life data block comprises the header of a network communications packet.

9. The method of claim 1 , further comprising caching data blocks that are not short life data blocks, wherein said data blocks are not restricted to the short life portion of the cache.

10. A system comprising:

a processor including a cache memory and a cache memory controller; and

a memory including one or more data blocks including at least one short life data block, the short life data block comprising short life data defined according to an expected operation of particular software, wherein the short life data is data that is anticipated to be used by the processor only for a short amount of time,

wherein the cache controller is configured to determine the short life data block from the one or more data blocks and store the short life data block only in a specific short life portion of the cache memory so that useful data in other portions of the cache memory is not to be replaced by short life data, the short life portion being of a lesser size than the entire cache memory.

11. A host bus adapter comprising the system of claim 10 .

12. A computer comprising the system of claim 10 .

13. A storage area network comprising the system of claim 10 .

14. A system comprising:

a processor including a cache memory and a cache memory controller; and

a memory including one or more data blocks including at least one short life data block, the short life data block comprising short life data defined according to an expected operation of particular software, wherein the short life data is data that is anticipated to be used by the processor only for a short amount of time,

wherein the processor is configured to access the data blocks in the memory and cause the cache controller to determine the short life data block from the one or more data blocks and store the short life data block only in a specific short life portion of the cache memory so that useful data in other portions of the cache memory is unlikely to be replaced by short life data, the short life portion being of a lesser size than the entire cache memory.

15. A host bus adapter comprising the system of claim 14 .

16. A computer comprising the system of claim 14 .

17. A storage area network comprising the system of claim 14 .

18. A system comprising:

a processor including a cache memory and a cache memory controller;

a memory including one or more data blocks including at least one short life data block, the short life data block comprising short life data defined according to an expected operation of particular software, wherein the short life data is data that is anticipated to be used by the processor only for a short amount of time, the memory further including computer executable instructions; and

a processor interface circuit coupled to the processor,

wherein the computer executable instructions, when executed at the processor, cause the cache controller to determine the short life data block from the one or more data blocks and store the short life data block only in a specific short life portion of the cache memory so that useful data in other portions of the cache memory is not to be replaced by short life data, the short life portion being of a lesser size than the entire cache memory.

19. The system of claim 18 , wherein the computer executable instructions, while executed at the processor, cause the processor to:

associate an actual memory address of the short life data block with a virtual address; and

generate a memory access command to access the virtual address.

20. The system of claim 19 , wherein the processor interface circuit is configured to:

intercept the memory access command referencing the virtual address and issued by the processor;

modify the memory access command by replacing the virtual address with the actual address of the short life data block in the memory access command; and

send the modified memory access command to the memory.

21. A host bus adapter comprising the system of claim 18 .

22. A computer comprising the system of claim 18 .

23. A storage area network comprising the system of claim 18 .

24. The system of claim 18 further comprising:

a network interface; and

a network link logic,

wherein the one or more data blocks comprise network communications data received through the network interface and stored in the memory by the network link logic.

25. The system of claim 24 , wherein the short life data block comprises headers of network communication packets.

26. A computer readable medium comprising computer executable instructions, said computer executable instructions, while executed at a processor, causing the processor to:

identify a data block as a short life data block;

translate an actual memory address of the short life data block into a virtual address, the virtual address being associated with a short life area of a cache memory, the short life area being smaller than the entire cache memory; and

attempt to access the short life data block using the virtual address, thus ensuring that in the event it is loaded into cache memory, the short life data block will be loaded into the short life area of the cache memory.

27. The computer readable medium of claim 26 , wherein the processor is an embedded processor and the computer executable instructions are firmware.

28. The computer readable medium of claim 26 , wherein the computer executable instructions are further configured to cause the processor to save an offset address in a register, the offset address being associated with an actual address of the short life data block and the virtual address, so that the actual address of the short life data block may be obtained from the virtual address and the offset address.