Hardware switch for hypervisors and blade servers

1. A hardware switch for enabling communications with one or more guest operating systems (OSs) in one or more servers, comprising:

a first memory configured for receiving a destination address (DA) and determining if the DA is accessible through the one or more servers;

a second memory coupled to the first memory and configured for receiving the DA and generating a routing rule to specify a route for the hardware switch if the DA is found in the first memory;

a third memory coupled to the first memory and configured for receiving a virtual local area network identifier (VLAN_ID) and generating a vector to specify a set of destination ports for the hardware switch if the DA is not found in the first memory;

a fourth memory to configure a set of ports within a given VLAN to be used by the hardware switch for broadcast media access control (MAC) DAs; and

a plurality of virtual ports (vPorts) implemented in hardware, each of one or more of the vPorts configured to be associated with a particular guest OS.

2. The hardware switch of claim 1 , further comprising:

a plurality of physical ports (pPorts) configured to provide network access.

3. The hardware switch of claim 2 , the hardware switch configured for receiving data from a peripheral component interconnect express (PCIe) bus, or any other host CPU attach communication protocol, through a vPort and selectively routing the data back to the PCIe bus or creating packets for transmission through a pPort.

4. The hardware switch of claim 2 , the vPorts and pPorts configured as having either a tagging port type for inserting or removing VLAN_IDs from incoming frames, an tagged port type for associating a default VLAN_ID with incoming frames, or a trunking port type.

5. The hardware switch of claim 1 , the hardware switch embedded in ingress and egress paths of a physical network interface card (pNIC).

6. The hardware switch of claim 5 , the pNIC further comprising a prefetch engine to prefetch transmit descriptors (TDs) from a guest OS into a transmit (Tx) queue.

7. The hardware switch of claim 6 , the TD including a source address (SA), destination address (DA), and VLAN number.

8. The hardware switch of claim 7 , the first memory comprising an egress port content addressable memory (CAM), the CAM being configured for receiving the VLAN number in addition to the DA to determine whether the DA is accessible through the one or more servers.

9. The hardware switch of claim 8 , the CAM configured to be programmable by a hypervisor in one of the servers.

10. The hardware switch of claim 5 , the pNIC further including a media access control (MAC) spoofing filter/engine configured for filtering packets using an access control list (ACL).

11. The hardware switch of claim 1 , the second memory comprising a rules random access memory (RAM) for providing a vector tuple including a virtual port (vPort) vector and a receive queue (RxQ) vector if the first memory determines that a received packet is a multicast match.

12. The hardware switch of claim 1 , the third memory comprising a multicast table, each entry in the multicast table representing a different destination port.

13. The hardware switch of claim 1 , further comprising logic configured for self-generating entries in the first memory as traffic is received by extracting a source address (SA) and noting a port at which the traffic was received.

14. The hardware switch of claim 1 , the hardware switch incorporated into a server.

15. The hardware switch of claim 1 , the hardware switch incorporated into a blade server.

16. The hardware switch of claim 1 , the hardware switch incorporated into a multi-root input/output virtualization (IOV) system.

17. The hardware switch of claim 1 , the hardware switch incorporated into a single-root input/output virtualization (IOV) system.

18. The hardware switch of claim 1 , the hardware switch incorporated into a host bus adapter (HBA).

19. The hardware switch of claim 1 , the hardware switch incorporated into a converged network adapter (CNA).

20. The hardware switch of claim 1 , the hardware switch incorporated into a network interface card (NIC).

21. A method within a physical network interface card (pNIC) for enabling communications with one or more guest operating systems (OSs) in one or more servers, comprising:

receiving a destination address (DA) and determining if the DA is accessible through the one or more servers;

generating a routing rule to specify a route if the DA is accessible through the one or more servers;

receiving a virtual local area network (VLAN) number and generating a tuple to specify a broadcast route if the DA not accessible through the one or more servers; and

providing a plurality of virtual ports (vPorts) implemented in hardware, each of one or more of the vPorts associated with a particular guest OS.

22. The method of claim 21 , further comprising:

providing a plurality of physical ports (pPorts) for network access.

23. The method of claim 22 , further comprising receiving data from a peripheral component interconnect express (PCIe) bus through a vPort and selectively routing the data back to the PCIe bus or creating packets for transmission through a pPort.

24. The method of claim 22 , further comprising assigning the vPorts and pPorts either a tagging port type for tagging VLAN numbers to or removing VLAN numbers from incoming frames, an untagged port type for appending a default VLAN entry to incoming frames, or a trunking port type.

25. The method of claim 21 , further comprising prefetching a transmit descriptor (TD) from a guest OS, the TD including a source address (SA), the DA, and VLAN number.

26. The method of claim 25 , wherein receiving a DA comprises receiving the VLAN number and the DA into an egress port content addressable memory (CAM) to determine whether the DA is accessible through the one or more servers.

27. The method of claim 26 , further comprising programming the CAM using a hypervisor in one of the servers.

28. The method of claim 21 , further comprising filtering received packets using an access control list (ACL).

29. The method of claim 21 , wherein generating a routing rule comprises providing a vector tuple including a virtual port (vPort) vector and a receive queue (RxQ) vector from a rules random access memory (RAM) if a received packet is a multicast match.

30. The method of claim 21 , further comprising self-generating data used for determining if the DA is accessible through the one or more servers as traffic is received by extracting a source address (SA) and noting a port at which the traffic was received.

31. The method of claim 21 , further comprising generating communication paths between different guest OSs running in the same server.

32. The method of claim 21 , further comprising generating communication paths between different guest OSs running in different server blades of a blade server.

33. A storage area network (SAN) including one or more servers, at least one of the servers having a physical network interface card (pNIC) including a hardware switch for enabling communications with one or more guest operating systems (OSs) in one or more of the servers, the hardware switch comprising:

a first memory configured for receiving a destination address (DA) and determining if the DA is accessible through the one or more servers;

a second memory coupled to the first memory and configured for receiving the DA and generating a routing rule to specify a route for the hardware switch if the DA is found in the first memory;

a third memory coupled to the first memory and configured for receiving a virtual local area network (VLAN) number and generating a tuple to specify a broadcast route for the hardware switch if the DA not found in the first memory; and

a plurality of virtual ports (vPorts) implemented in hardware, each of one or more of the vPorts configured to be associated with a particular guest OS.