Enhanced I/O performance in a multi-processor system via interrupt affinity schemes
View Patent ↗Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.
1. A system for controlling interrupt processing, the system comprising:
an adapter operable to generate an interrupt, wherein the interrupt is communicated over a channel selected from a plurality of channels and the interrupt is processed by a processor selected from a plurality of processors,
wherein the processor is selected according to a first mapping and the channel is selected according to a second mapping,
wherein the first mapping comprises an association between the processor and the interrupt, wherein the interrupt is mapped to the processor that requested an operation triggering the interrupt, the first mapping having a first group of assignments between one or more processors of the plurality of processors and a plurality of respective interrupt identifiers, and
wherein the second mapping comprises an association between the interrupt and the channel and the second mapping is adaptable based on a usage of one or more processors of the plurality of processors as assigned in the first mapping, the second mapping having a second group of assignments between the plurality of respective interrupt identifiers and one or more channels of the plurality of channels.
2. The system of claim 1 , wherein the adapter comprises a network adapter that is operable to communicate with a Storage Area Network (SAN) over a number of communication links, the communication links comprising one or both of: Fibre Channel links and Ethernet links.
3. The system of claim 1 , wherein the system comprises:
a plurality of Local Advanced Programmable Interrupt Controllers (LAPICs), each LAPIC of the plurality of LAPICs is associated with a processor of the plurality of processors, wherein a LAPIC of the plurality of LAPICs is operable to assist with processing an interrupt; and
a plurality of caches, each cache of the plurality of caches is associated with a LAPIC of the plurality of LAPICs, wherein a cache of the plurality of caches is operable to store interrupt-related instructions accessible by an LAPIC and a processor associated with the cache.
4. The system of claim 1 , wherein the system comprises an Input/Output Advanced Programmable Interrupt Controller (I/O APIC) hub being operable to manage the interrupts received from the adapter.
5. An adapter for controlling interrupt processing, the adapter comprising:
a worker kernel thread operable to handle an interrupt; and
an interrupt thread operable to wake up the worker kernel thread,
wherein the interrupt is communicated over a channel selected from a plurality of channels and the interrupt is processed by a processor selected from a plurality of processors,
wherein the processor is selected according to a first mapping and a second mapping, the first mapping having a first group of assignments between one or more processors of the plurality of processors and a plurality of respective interrupt identifiers, the second mapping having a second group of assignments between the plurality of respective interrupt identifiers and one or more channels of the plurality of channels, the second mapping being adaptable based on a usage of the first mapping.
6. The adapter of claim 5 , wherein interrupt thread is operable to transfer a process to the worker kernel thread, the process being associated with the interrupt.
7. The adapter of claim 5 , wherein the interrupt is associated with an interrupt identifier of a plurality of interrupt identifiers, the worker kernel thread is generated for handling interrupts having a particular interrupt identifier.
8. The adapter of claim 7 , wherein the worker kernel thread is bound to the processor in accordance with the particular interrupt identifier.
9. The adapter of claim 5 , wherein the worker kernel thread is placed in a thread queue associated with the processor, the worker kernel thread being initiated when the interrupt is received at the processor.
10. The adapter of claim 5 , wherein the worker kernel thread is serviced by the processor when a priority of the worker kernel thread becomes current and the worker kernel thread is ready to be serviced by the processor.
11. The adapter of claim 5 , wherein the adapter is operable to generate the interrupt.
12. The adapter of claim 5 , wherein the adapter is operable to communicate with a Storage Area Network (SAN) over a number of communication links.
13. A method for controlling interrupt processing, the method comprising:
generating an interrupt;
selecting a processor from a plurality of processors according to the interrupt and a first mapping, the first mapping having a first group of assignments between one or more processors of a plurality of processors and a plurality of respective interrupt identifiers;
communicating the interrupt over a selected channel according to a second mapping, the second mapping having a second group of assignments between the plurality of respective interrupt identifiers and one or more channels of a plurality of channels, the second mapping being adaptable based on a usage of the first mapping;
waking up a worker kernel thread; and
handling the interrupt by the worker kernel thread associated with the processor.
14. The method of claim 13 , wherein handling the interrupt by the worker kernel thread associated with the processor comprises transferring a process to the worker kernel thread, the process being associated with the interrupt.
15. The method of claim 13 , comprising:
associating the interrupt with an interrupt identifier of a plurality of interrupt identifiers; and
generating the worker kernel thread for handling interrupts having a particular interrupt identifier.
16. The method of claim 15 , comprising binding the worker kernel thread to the processor in accordance with the particular interrupt identifier.
17. The method of claim 13 , comprising:
placing the worker kernel thread in a thread queue associated with the processor; and
initiating the worker kernel thread in the thread queue when the interrupt is received at the processor.
18. The method of claim 13 , comprising servicing the worker kernel thread by the processor when a priority of the worker kernel thread becomes current and the worker kernel thread is ready to be serviced by the processor.
19. The method of claim 13 , comprising generating the interrupt by a host bus adapter.
20. The method of claim 19 , comprising communicating between the host bus adapter and a Storage Area Network (SAN).