Virtual peripheral component interconnect multiple-function device
View Patent ↗A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function logic. Each set of configuration space registers is associated with a function. The virtual multiple-function logic is coupled to the bus interface and the configuration space register sets. The virtual multiple-function logic provides access to a plurality of configuration space registers for a plurality of functions. The virtual multiple-function logic also enables a plurality of functions to share the bus interface and other internal logic.
1. A device comprising:
a bus interface coupled to a component interconnect bus and being associated with a communications standard;
a plurality of configuration space register sets, each configuration space register set being associated with a function of the device; and
multiple-function logic coupled to the bus interface and the configuration space register sets, the multiple-function logic being adapted to coordinate the communications of a plurality of functions of the device over the component interconnect bus in accordance with the communications standard,
wherein each function corresponds to a set of behaviors which is treated by the communications standard as an separate entity.
2. The device of claim 1 , wherein the bus interface is a Peripheral Component Interconnect bus interface coupled to a Peripheral Component Interconnect bus, and the communications protocol is the Peripheral Component Interconnect standard.
3. The device of claim 1 , wherein the multiple-function logic is adapted to handle a plurality of Peripheral Component Interconnect functions.
4. The device of claim 1 , wherein the bus interface is a Peripheral Component Interconnect Extended (PCI-X) bus interface coupled to a Peripheral Component Interconnect Extended bus and the communications protocol is the PCI-X standard.
5. The device of claim 1 , wherein the device is an application specific integrated circuit.
6. The device of claim 1 , wherein each set of configuration space registers comprises a command register, the multiple-function logic using bits from a plurality of command registers associated with a plurality of functions to control the device.
7. The device of claim 1 , wherein each set of configuration space registers comprises a status register, the multiple-function logic using bits from a plurality of status registers associated with a plurality of functions to control the device.
8. The device of claim 1 , wherein each set of configuration space registers comprises a cache line size register, the multiple-function logic using bits from a plurality of cache line size registers associated with a plurality of functions to control the device.
9. The device of claim 1 , wherein each set of configuration space registers comprises latency timer register, the multiple-function logic using bits from a plurality of latency timer registers associated with a plurality of functions to control the device.
10. The device of claim 1 , wherein each set of configuration space registers comprises a Peripheral Component Interconnect Extended (PCI-X) command register, the multiple-function logic using bits from a plurality of Peripheral Component Interconnect Extended (PCI-X) command registers associated with a plurality of functions to control the device.
11. The device of claim 1 , wherein each set of configuration space registers comprises a Peripheral Component Interconnect Extended (PCI-X) status register, the multiple-function logic using bits from a plurality of Peripheral Component Interconnect Extended (PCl-X) status registers associated with a plurality of functions to control the device.
12. The device of claim 1 , wherein the multiple-function logic coordinates a plurality of configuration space registers for a plurality of functions.
13. The device of claim 1 , wherein the multiple-function logic enables a plurality of functions to share the bus interface.
14. The device of claim 1 , wherein the multiple-function logic enables a plurality of functions to share internal device logic.
15. The device of claim 1 , wherein the multiple-function logic enables a plurality of functions to share internal resources of the device.
16. The device of claim 1 , further comprising a Peripheral Component Interconnect Extended (PCI-X) master interface logic shared by a plurality of functions.
17. The device of claim 1 , further comprising a Peripheral Component Interconnect Extended (PCI-X) slave interface logic shared by a plurality of functions.
18. The device of claim 1 , further comprising control registers shared by a plurality of functions.
19. The device of claim 1 , further comprising a processing unit shared by a plurality of functions.
20. The device of claim 1 , further comprising a memory shared by a plurality of functions.
21. The device of claim 1 , further comprising a direct memory access controller shared by a plurality of functions.
22. A system comprising:
a host processor;
a local bus coupled to the host processor and being associated with a communications standard; and
a multiple-function device coupled to the local bus, the multiple-function device comprising:
a bus interface, connected to the communications bus and being associated with the communications standard;
a plurality of configuration space register sets, each configuration space register set being associated with a function of the multiple-function device; and
multiple-function logic coupled to the bus interface and the configuration space register sets, the multiple-function logic being adapted to coordinate the communications of a plurality of functions of the device, over the component interconnect bus in accordance with the communications standard,
wherein each function corresponds to a set of behaviors which is treated by the communications standard as an separate entity.