System and method for routing data

1. An apparatus comprising:

a communication interface operable to communicate data;

a first-input-first-output buffer (FIFO) operably connected to the communication interface and operable to buffer data; and

a processor module operably connected to the FIFO, the processor module comprising route determination logic comprising a state machine, wherein the state machine has a plurality of modes of operation including:

a first mode of operation that monitors for signals,

a second mode of operation that indicates a route request for the processor module,

a third mode of operation that decodes to determine a route of a plurality of routes, wherein each of the plurality of routes comprises the FIFO, and

a fourth mode of operation that indicates the processor module will wait until more data is received before routing data out of the FIFO.

2. The apparatus of claim 1 , wherein the communication interface is a port.

3. The apparatus of claim 1 , wherein the communication interface is an Ethernet port.

4. The apparatus of claim 1 , wherein the FIFO buffers data received from the communication interface.

5. The apparatus of claim 1 , wherein the FIFO buffers data to be transmitted from the communication interface.

6. The apparatus of claim 1 , wherein the processor module operates according to a signaling protocol.

7. The apparatus of claim 1 , wherein the processor module guards against a receive FIFO overrun condition.

8. The apparatus of claim 1 , wherein the processor module comprises a direct memory access (DMA) module.

9. A system for routing data, the system comprising:

a communication interface operable to communicate data;

a first-input-first-output buffer (FIFO) operably connected to the communication interface and operable to buffer the communicated data; and

a processor module operably connected to the FIFO, the processor module being operable to:

monitor the buffered data,

decode a route of a plurality of routes according to the buffered data, wherein each of the plurality of routes comprises the FIFO, and

move the buffered data according to the route and the amount of data in the FIFO.

10. The system of claim 9 , wherein the communication interface is a port.

11. The system of claim 9 , wherein the communication interface is an Ethernet port.

12. The system of claim 9 , wherein the FIFO buffers data received from the communication interface.

13. The system of claim 9 , wherein the FIFO buffers data to be transmitted from the communication interface.

14. The system of claim 9 , wherein the processor module operates according to a signaling protocol.

15. The system of claim 9 , wherein the processor module guards against a receive FIFO overrun condition.

16. The system of claim 9 , wherein the processor module comprises a direct memory access (DMA) module.

17. The system of claim 9 , wherein the processor module is operable to monitor for received data.

18. The system of claim 9 , wherein the processor module is operable to monitor for data to be transmitted.

19. A method for routing data, the method comprising:

receiving data;

buffering the received data in a FIFO;

determining a route of a plurality of routes according to a header within the buffered data, wherein each of the plurality of routes comprises the FIFO;

determining whether a sufficient amount of data is buffered; and

moving the buffered data according to the route and whether a sufficient amount of data is buffered.

20. The method of claim 19 , wherein the received data is from an Ethernet network.