Supercharge message exchanger
View Patent ↗A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
1. A method comprising:
receiving input/output (I/O) completions from a plurality of data paths, the plurality of data paths including first processor data paths for I/O completions resulting from I/O requests initiated by a first processor, and a write data path for I/O completions resulting from I/O requests initiated by a second processor; storing the I/O completions in a plurality of registers, each register being configured to store an I/O completion from one of the plurality of data paths;
transferring the I/O completions from the plurality of registers to a plurality of logical blocks of a random access memory, each logical block being configured to store I/O completions from one of the plurality of data paths, wherein each respective register and each respective logical block are associated with a respective predetermined one of the plurality of data paths; and
processing the I/O completions stored in the plurality of logical blocks using the first processor, including the I/O completions resulting from the I/O requests initiated by the second processor.
2. The method of claim 1 , wherein receiving input/output (I/O) completions from the plurality of data paths comprises receiving I/O completions from a first set of data paths in a first mode, and receiving I/O completions from a second set of data paths in a second mode.
3. The method of claim 1 , further comprising:
transferring the I/O completions from the registers to an arbitrator;
arbitrating which I/O completion to send to a selected one of the plurality of logical blocks of the random access memory; and
sending one of the I/O completions from the arbitrator to the selected logical block of the random access memory.
4. The method of claim 3 , wherein arbitrating involves using a round robin method.
5. The method of claim 1 , further comprising sending a plurality of ready signals to a plurality of data sources via the plurality of data paths, each ready signal indicating that a selected one of the plurality of registers is ready to store one of the I/O completions.
6. The method of claim 5 , further comprising detecting one of the plurality of ready signals and generating a write-enable signal if one of the plurality of data sources has a particular I/O completion to write to the random access memory.
7. The method of claim 1 , further comprising using pointers to determine if there are outstanding I/O completions ready for processing.
8. The method of claim 1 , further comprising using pointers to determine whether one or more of the plurality of logical blocks is full.
9. The method of claim 8 , further comprising preventing one of the I/O completions from being written to a selected one of the plurality of logical blocks if the selected logical block is full.
10. The method of claim 8 , further comprising notifying a source coupled to one of the plurality of data paths that the logical block and register configured to store I/O completions from the source are full.