Optimization of abutted-pin hierarchical physical design
View Patent ↗An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.
1. A method of improving a physical design of a current integrated circuit, comprising the steps of:
a) receiving a netlist of said current integrated circuit;
b) receiving physical design information from a prior integrated circuit; and
c) generating said physical design based on said netlist and said physical design information.
2. A method as recited in claim 1 wherein said physical design information includes pin assignments of blocks of said prior integrated circuit.
3. A method as recited in claim 1 wherein said physical design information includes optimal clock distribution tree of said prior integrated circuit.
4. A method as recited in claim 1 wherein said physical design information includes parasitic extraction data of said prior integrated circuit.
5. A method as recited in claim 1 wherein said physical design information includes identification of congested blocks of said prior integrated circuit.
6. A method as recited in claim 1 wherein said physical design information includes metal resources of said prior integrated circuit.
7. A method as recited in claim 1 wherein said physical design information includes information which facilitates optimizing said current integrated circuit.
8. A method as recited in claim 1 wherein said step c) includes:
generating a top-level physical design of said current integrated circuit using said netlist and said physical design information including block-level physical design information of said prior integrated circuit.
9. A method as recited in claim 1 wherein said step c) includes:
generating a block-level physical design of said current integrated circuit using said netlist and said physical design information including block-level physical design information of said prior integrated circuit.
10. A method as recited in claim 1 wherein said physical design is an abutted-pin hierarchical physical design including a top-level physical design and a block-level physical design.
11. A method as recited in claim 1 wherein said physical design information includes locations of obstructions of said prior integrated circuit.
12. A method as recited in claim 11 wherein said obstructions include a random access memory (RAM).
13. A method as recited in claim 1 wherein said step c) includes:
partitioning said netlist into a plurality of blocks, each block including a block-level netlist;
performing a top-level floor planning;
performing a top-level placement and route for a plurality of top-level objects;
performing a top-level placement and route for a plurality of ports from said blocks to determine pin assignments for each block; and
generating and optimizing a block-level physical design for each block in parallel.
14. A method as recited in claim 13 wherein said generating and optimizing includes:
pressing each portion of each top-level object, which is located within a boundary of a particular block, into said particular block;
generating each pin for each block based on said top-level placement and route to determine pin assignments;
performing a block-level floor planning for each block;
performing a block-level placement for each block;
performing a plurality of block-level operations to optimize each block; and
performing a block-level route for each block.
15. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of improving a physical design of a current integrated circuit, said method comprising:
a) receiving a netlist of said current integrated circuit;
b) receiving physical design information from a prior integrated circuit; and;
c) generating said physical design based on said netlist and said physical design information.
16. A computer-readable medium as recited in claim 15 wherein said physical design information includes pin assignments of blocks of said prior integrated circuit.
17. A computer-readable medium as recited in claim 15 wherein said physical design information includes optimal clock distribution tree of said prior integrated circuit.
18. A computer-readable medium as recited in claim 15 wherein said physical design information includes parasitic extraction data of said prior integrated circuit.
19. A computer-readable medium as recited in claim 15 wherein said physical design information includes identification of congested blocks of said prior integrated circuit.
20. A computer-readable medium as recited in claim 15 wherein said physical design information includes metal resources of said prior integrated circuit.
21. A computer-readable medium as recited in claim 15 wherein said physical design information includes information which facilitates optimizing said current integrated circuit.
22. A computer-readable medium as recited in claim 15 wherein said step c) includes:
generating a top-level physical design of said current integrated circuit using said netlist and said physical design information including block-level physical design information of said prior integrated circuit.
23. A computer-readable medium as recited in claim 15 wherein said step c) includes:
generating a block-level physical design of said current integrated circuit using said netlist and said physical design information including block-level physical design information of said prior integrated circuit.
24. A computer-readable medium as recited in claim 15 wherein said physical design is an abutted-pin hierarchical physical design including a top-level physical design and a block-level physical design.
25. A computer-readable medium as recited in claim 15 wherein said physical design information includes locations of obstructions of said prior integrated circuit.
26. A computer-readable medium as recited in claim 25 wherein said obstructions include a random access memory (RAM).
27. A computer-readable medium as recited in claim 15 wherein said step c) includes:
partitioning said netlist into a plurality of blocks, each block including a block-level netlist;
performing a top-level floor planning;
performing a top-level placement and route for a plurality of top-level objects;
performing a top-level placement and route for a plurality of ports from said blocks to determine pin assignments for each block; and
generating and optimizing a block-level physical design for each block in parallel.
28. A computer-readable medium as recited in claim 27 wherein said generating and optimizing includes:
pressing each portion of each top-level object, which is located within a boundary of a particular block, into said particular block;
generating each pin for each block based on said top-level placement and route to determine pin assignments;
performing a block-level floor planning for each block;
performing a block-level placement for each block;
performing a plurality of block-level operations to optimize each block; and
performing a block-level route for each block.
29. A method of determining a plurality of pins for each block of a physical design of a current integrated circuit, comprising:
a) receiving a netlist of said current integrated circuit;
b) receiving physical design information from a prior integrated circuit, wherein said physical design information includes pin assignments of blocks of said prior integrated circuit;
c) using said netlist and said physical design information to perform a top-level placement for a plurality of ports corresponding to each block of said current integrated circuit;
d) using said netlist and said physical design information to perform a top-level route for said ports to determine pin assignments for each block of said current integrated circuit; and
e) generating each pin for each block based on said top-level route to determine pin assignments.
30. A method as recited in claim 29 further comprising:
partitioning said netlist into a plurality of blocks of said current integrated circuit, each block including a block-level netlist.
31. A method as recited in claim 29 wherein said physical design information includes optimal clock distribution tree of said prior integrated circuit.
32. A method as recited in claim 29 wherein said physical design information includes parasitic extraction data of said prior integrated circuit.
33. A method as recited in claim 29 wherein said physical design information includes identification of congested blocks of said prior integrated circuit.
34. A method as recited in claim 29 wherein said physical design information includes metal resources of said prior integrated circuit.
35. A method as recited in claim 29 wherein said physical design information includes information which facilitates optimizing said current integrated circuit.
36. A method as recited in claim 29 wherein said physical design information includes locations of obstructions of said prior integrated circuit.
37. A method as recited in claim 36 wherein said obstructions include a random access memory (RAM).
38. A method as recited in claim 29 wherein said physical design is an abutted-pin hierarchical physical design.
39. A method as recited in claim 38 wherein said physical design includes a top-level physical design.
40. A method as recited in claim 38 wherein said physical design includes a block-level physical design.
41. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of determining a plurality of pins for each block of a physical design of a current integrated circuit, comprising:
a) receiving a netlist of said current integrated circuit;
b) receiving physical design information from a prior integrated circuit, wherein said physical design information includes pin assignments of blocks of said prior integrated circuit;
c) using said netlist and said physical design information to perform a top-level placement for a plurality of ports corresponding to each block of said current integrated circuit;
d) using said netlist and said physical design information to perform a top-level route for said ports to determine pin assignments for each block of said current integrated circuit; and
e) generating each pin for each block based on said top-level route to determine pin assignments.
42. A computer-readable medium as recited in claim 41 wherein said method further comprises:
partitioning said netlist into a plurality of blocks of said current integrated circuit, each block including a block-level netlist.
43. A computer-readable medium as recited in claim 41 wherein said physical design information includes optimal clock distribution tree of said prior integrated circuit.
44. A computer-readable medium as recited in claim 41 wherein said physical design information includes parasitic extraction data of said prior integrated circuit.
45. A computer-readable medium as recited in claim 41 wherein said physical design information includes identification of congested blocks of said prior integrated circuit.
46. A computer-readable medium as recited in claim 41 wherein said physical design information includes metal resources of said prior integrated circuit.
47. A computer-readable medium as recited in claim 41 wherein said physical design information includes information which facilitates optimizing said current integrated circuit.
48. A computer-readable medium as recited in claim 41 wherein said physical design information includes locations of obstructions of said prior integrated circuit.
49. A computer-readable medium as recited in claim 48 wherein said obstructions include a random access memory (RAM).
50. A computer-readable medium as recited in claim 41 wherein said physical design is an abutted-pin hierarchical physical design.
51. A computer-readable medium as recited in claim 50 wherein said physical design includes a top-level physical design.
52. A computer-readable medium as recited in claim 50 wherein said physical design includes a block-level physical design.