Patent Assignment
Reel/Frame 040607/0632
Release of Security Interest
Recorded: 2016-11-11
Pages: 20
Assignor
WELLS FARGO CAPITAL FINANCE, LLC
Executed: 2016-10-31
Assignee
SYNOPSYS, INC.
690 EAST MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(99)
A Method for Automatic Clock Gating to Save Power
PCT:
PCT/US2008/065120 ↗
Cad Driven Microprobe Integrated Circuit Tester
Patent:
5,030,907 →
Application:
07/354,268 →
Contact Sensing for Integrated Circuit Testing
Patent:
5,019,771 →
Application:
07/527,661 →
A Method of Automating the Manipulation and Display of Sets of Wafer Yield Data Using a User Interface Smart Macro.
Patent:
6,088,712 →
Application:
08/994,996 →
Creating Optimized Physical Implementations from High-Level Descriptions of Electronic Design Using Placement Based Information.
Patent:
6,145,117 →
Application:
09/015,602 →
Method and System for Creating Electronic Circuitry
Patent:
6,327,557 →
Application:
09/090,457 →
Ic Test Software System for Mapping Logical Functional Test Data of Logic Integrated Circuits to Physical Representation
Patent:
6,185,707 →
Application:
09/192,164 →
Method for Forming a Structural Similarity Group from a Netlist of an Integrated Circuit
Patent:
6,606,737 →
Application:
09/293,484 →
Method for Determining Cleanup Line Routing for Components of an Integrated Circuit
Patent:
6,438,736 →
Application:
09/293,485 →
Method for Determining Control Line Routing for Components of an Integrated Circuit
Patent:
6,687,892 →
Application:
09/293,488 →
Method for Forming a Relative Placement of Components of an Integrated Circuit Using a Structural Similarity Group
Patent:
6,584,605 →
Application:
09/293,500 →
Method for Determining Bus Line Routing for Components of an Integrated Circuit
Patent:
6,430,734 →
Application:
09/293,638 →
Method for Modifying Placement of Components of an Integrated Circuit by Analyzing Resources of Adjacent Components
Patent:
6,434,734 →
Application:
09/293,640 →
Generalized Theory of Logical Effort for Look-Up Table Based Delay Models
Patent:
6,253,361 →
Application:
09/295,938 →
Method for Storing Multiple Levels of Design Data in a Common Dabase
Patent:
6,505,328 →
Application:
09/300,540 →
Timing Optimization in Presence of Interconnect Delays
Patent:
6,553,338 →
Application:
09/300,557 →
Subgrid Detailed Routing
Patent:
6,507,941 →
Application:
09/301,143 →
Method of Estimating Performance of Integrated Circuit Designs
Patent:
6,499,129 →
Application:
09/357,940 →
Automated Design of Parallel Drive Standard Cells
Patent:
6,496,965 →
Application:
09/399,986 →
Method for Providing Convex Piecewise-Linear Expression for Multiple Variable System
Patent:
6,813,590 →
Application:
09/475,734 →
System and Method for Performing Assertion-Based Analysis of Circuit Designs
Patent:
6,591,402 →
Application:
09/528,088 →
System and Method for Estimating Capacitance of Wires Based on Congestion Information
Patent:
6,519,745 →
Application:
09/579,966 →
Creating Optimized Physical Implementations from High-Level Descriptions of Electronic Design Using Placement-Based Information
Patent:
6,360,356 →
Application:
09/634,927 →
Interconnect Model Compiler
Patent:
6,766,506 →
Application:
09/707,757 →
Method and System for Automatically Generating Low Level Program Commands as Dependency Graphs from High Level Physical Design Stages
Patent:
6,574,788 →
Application:
09/712,418 →
Method and System for Implementing a User Interface for Performing Physical Design Operations on an Integrated Circuit Netlist
Patent:
6,557,153 →
Application:
09/714,296 →
Optimization of Abutted-Pin Hierarchical Physical Design
Patent:
6,857,116 →
Application:
09/714,722 →
Methodology and Applications of Timing-Driven Logic Resysnthesis for Vlsi Circuits
Patent:
7,219,048 →
Application:
09/754,406 →
Method and Apparatus for Calculation of Crosstalk Noise in Integrated Circuits
Patent:
7,013,253 →
Application:
09/823,085 →
Optimal Simultaneous Design and Floorplanning of Integrated Circuit
Rapid Parameter Passing Between Multiple Program Portions for Efficient Procedural Interaction with Minimum Calls and/or Call Backs
Apparatus for Optimized Constraint Characterization with Degradation Options and Associated Methods
Method and System for Implementing a Graphical User Interface for Depicting Loose Fly Line Interconnections Between Multiple Blocks of an Integrated Circuit Netlist
Patent:
6,553,554 →
Application:
09/908,957 →
Method and System for Implementing a Graphical User Interface for Defining and Linking Multiple Attach Points for Multiple Blocks of an Integrated Circuit Netlist
Patent:
6,564,363 →
Application:
09/909,050 →
Method and System for Maintaining Element Abstracts of an Integrated Circuit Netlist Using a Master Library File and Modifiable Master Library File
Patent:
6,564,364 →
Application:
09/909,354 →
Method of Incremental Recharacterization to Estimate Performance of Integrated Circuit Designs
Patent:
6,851,095 →
Application:
09/999,222 →
Creating Optimized Physical Implementations from High-Level Descriptions of Electronic Design Using Placement-Based Information
System and Method for Limiting Increase in Capacitance Due to Dummy Metal Fills Utilized for Improving Planar Profile Uniformity
Patent:
6,751,785 →
Application:
10/097,978 →
Facilitating Verification in Abutted-Pin Hierarchical Physical Design
Patent:
6,757,874 →
Application:
10/104,786 →
Optimization of the Top Level in Abutted-Pin Heirarchical Physical Design
Patent:
6,865,721 →
Application:
10/104,960 →
Behavioral circuit modeling for geometric programming
Application:
10/118,221 →
Publication:
US 2003/0191611
Method and Apparatus for Automatic Analog/Mixed Signal System Design Using Geometric Programming
Method and Apparatus for Routing an Integrated Circuit
Patent:
6,877,148 →
Application:
10/118,673 →
Efficient Layout Strategy for Automated Design Layout Tools
Method and Apparatus for Automatic Layout of Circuit Structures
Patent:
6,789,246 →
Application:
10/119,326 →
Automatic Phase Lock Loop Design Using Geometric Programming
System and Method for Placement of Dummy Metal Fills While Preserving Device Matching and/or Limiting Capacitance Increase
Patent:
6,904,581 →
Application:
10/158,617 →
Method for Generating Design Constraints for Modules in a Hierarchical Integrated Circuit Design System
Representing the Design of a Sub-Module in a Hierarchical Integrated Circuit Design and Analysis System
Method of Customizing and Using Maps in Generating the Padring Layout Design
Patent:
6,734,046 →
Application:
10/264,679 →
Method of Generating the Padring Layout Design Using Automation
Patent:
6,823,501 →
Application:
10/264,680 →
Method of Optimizing Placement and Routing of Edge Logic in Padring Layout Design
Patent:
7,117,469 →
Application:
10/264,691 →
Methodology for Design of Oscillator Delay Stage and Corresponding Applications
Patent:
7,039,885 →
Application:
10/348,723 →
Delay Stage for Oscillator Circuit and Corresponding Applications
Patent:
7,102,449 →
Application:
10/348,822 →
Method and Apparatus for Efficient Semiconductor Process Evaluation
Analog Circuit Power Distribution Circuits and Design Methodologies for Producing Same
Patent:
7,013,436 →
Application:
10/444,602 →
Capacitor Structure and Automated Design Flow for Incorporating Same
Patent:
6,963,122 →
Application:
10/656,793 →
Design-Manufacturing Interface via a Unified Model
Reduction of Cross-Talk Noise in Vlsi Circuits
Automatic Phase Lock Loop Design Using Geometric Programming
Reduced Architecture Processing Paths
Patent:
7,137,082 →
Application:
10/812,579 →
Modeling Interconnected Propagation Delay for an Integrated Circuit Design
Patent:
7,213,221 →
Application:
10/827,791 →
Floorplanning a Hierarchical Physical Design to Improve Placement and Routing
Patent:
7,155,693 →
Application:
10/831,700 →
Creating a Power Distribution Arrangement with Tapered Metal Wires for a Physical Design
Patent:
7,185,305 →
Application:
10/855,539 →
Optimizing Locations of Pins for Blocks in a Hierarchical Physical Design by Using Physical Design Information of a Prior Hierarchical Physical Design
Patent:
7,114,142 →
Application:
10/855,667 →
Flow Definition Language for Designing Integrated Circuit Implementation Flows
Patent:
7,353,488 →
Application:
10/856,268 →
Asynchronous Control of Memory Self Test
Patent:
7,203,873 →
Application:
10/861,247 →
Redundantly Tied Metal Fill for Ir-Drop and Layout Density Optimization
Patent:
7,240,314 →
Application:
10/861,812 →
Method of Using Strongly Coupled Components to Estimate Integrated Circuit Performance
Patent:
7,337,416 →
Application:
10/880,649 →
Method of Estimating Performance of Integrated Circuit Designs by Finding Scalars for Strongly Coupled Components
Patent:
7,340,698 →
Application:
10/881,195 →
Method of Vector Generation for Estimating Performance of Integrated Circuit Designs
Patent:
7,000,202 →
Application:
10/881,832 →
Method of Estimating Performance of Integrated Circuit Designs Using State Point Identification
Patent:
7,117,461 →
Application:
10/882,003 →
Circuit Optimization with Posynomial Function F Having an Exponent of a First Design Parameter
Parametric Timing Analysis
Patent:
7,346,874 →
Application:
11/048,287 →
Methods and Systems for Mixed-Mode Physical Synthesis in Electronic Design Automation
Rule-based design consultant and method for integrated circuit design
Application:
11/141,386 →
Publication:
US 2005/0268258
Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information
Application:
11/262,736 →
Publication:
US 2006/0053396
Sensitivity-current-based model for equivalent waveform propagation in the presence of noise for static timing analysis
Application:
11/264,919 →
Publication:
US 2006/0112357
Lithographically Optimized Placement Tool
Patent:
7,434,188 →
Application:
11/372,557 →
Aggregate Sensitivity for Statistical Static Timing Analysis
Patent:
7,458,049 →
Application:
11/451,905 →
Signal Flow Driven Circuit Analysis and Partitioning Technique
Placement-Driven Physical-Hierarchy Generation
Application:
11/734,757 →
Publication:
US 2007/0245281
Relative Floorplanning For Improved Integrated Circuit Design
Application:
11/748,416 →
Publication:
US 2007/0266359
Lithography Aware Leakage Analysis
Lithography Aware Timing Analysis
Novel Optimization for Circuit Design
Novel Optimization for Circuit Design
Parser for signomial and geometric programs
Application:
11/986,253 →
Publication:
US 2008/0072215
Method for Storing Multiple Levels of Design Data in a Common Database
Application:
12/113,834 →
Publication:
US 2008/0209364
Method for Automatic Clock Gating to Save Power
Method for Optimized Automatic Clock Gating
Method for Repeated Block Timing Analysis
Patent:
7,971,168 →
Application:
12/128,919 →
Method for Repeated Block Modification for Chip Routing
Patent:
8,407,650 →
Application:
12/129,916 →
Dynamic Push for Topological Routing of Semiconductor Packages
Patent:
8,006,216 →
Application:
12/134,849 →
Timing Analysis Using Statistical on-Chip Variation
Patent:
7,992,114 →
Application:
12/135,031 →
Multi-Threaded Global Routing
Patent:
8,234,614 →
Application:
12/156,963 →
Method for Multi-Cycle Path and False Path Clock Gating
Patent:
7,958,476 →
Application:
12/170,354 →
Automated Circuit Design Using Active Set Solving Process
Patent:
8,307,309 →
Application:
12/195,326 →
Structured Placement For Bit Slices
Related Assignments
(8)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name
Jun 5, 2012
From: MAGMA DESIGN AUTOMATION, INC.
To: MAGMA DESIGN AUTOMATION LLC
Reel/Frame 028323/0056 →
Assignment of Assignor's Interest
Jun 5, 2012
From: MAGMA DESIGN AUTOMATION LLC
To: SYNOPSYS, INC.
Reel/Frame 028323/0064 →
Nunc Pro Tunc Assignment
Oct 19, 2012
From: MAGMA DESIGN AUTOMATION LLC
To: SYNOPSYS, INC.
Reel/Frame 029161/0846 →
Assignment of Assignor's Interest
Jun 22, 2016
From: FORMFACTOR, INC.
To: MARTEK, INC.
Reel/Frame 039117/0281 →
Nunc Pro Tunc Assignment
Feb 24, 2017
From: MAGMA DESIGN AUTOMATION LLC
To: SYNOPSYS, INC.
Reel/Frame 041367/0705 →
Change of Name
Feb 27, 2017
From: MAGMA DESIGN AUTOMATION, INC.
To: MAGMA DESIGN AUTOMATION LLC
Reel/Frame 041823/0624 →
Change of Name
Mar 16, 2017
From: MAGMA DESIGN AUTOMATION, INC.
To: MAGMA DESIGN AUTOMATION LLC
Reel/Frame 042023/0876 →
Change of Name
Sep 2, 2020
From: MAGMA DESIGN AUTOMATION, INC.
To: MAGMA DESIGN AUTOMATION LLC
Reel/Frame 053669/0442 →