Optimization of the top level in abutted-pin hierarchical physical design
View Patent ↗An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.
1. A method of optimizing determination of pins for a plurality of blocks of a physical design, comprising:
a) determining a plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells;
b) at a top-level, placing each one of said plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement;
c) at said top-level, routing said ports using a routing wire;
d) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks; and
e) removing one or more excess pins from said plurality of blocks based on criteria.
2. A method as recited in claim 1 wherein said criteria includes current flow direction between a source port of a first block and a destination port of a second block.
3. A method as recited in claim 1 wherein said criteria includes location of excess pins relative to a source port of a first block and a destination port of a second block.
4. A method as recited in claim 1 wherein said physical design is an abutted-pin hierarchical physical design.
5. A method as recited in claim 4 wherein said physical design includes a top-level physical design.
6. A method as recited in claim 4 wherein said physical design includes a block-level physical design.
7. A method as recited in claim 1 wherein said step by d) includes:
at each location along a boundary between a first block and a second block in which a route path between a source port of said first block and a destination port of said second block crosses said boundary, forming a first pin for said first block and forming a second pin for said second block, wherein said first and second pins are abutted.
8. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of optimizing determination of pins for a plurality of blocks of a physical design, said method comprising:
a) determining a plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells;
b) at a top-level, placing each one of said plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement;
c) at said top-level, routing said ports using a routing wire;
d) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks; and
e) removing one or more excess pins from said plurality of blocks based on criteria.
9. A computer-readable medium as recited in claim 8 wherein said criteria includes current flow direction between a source port of a first block and a destination port of a second block.
10. A computer-readable medium as recited in claim 8 wherein said criteria includes location of excess pins relative to a source port of a first block and a destination port of a second block.
11. A computer-readable medium as recited in claim 8 wherein said physical design is an abutted-pin hierarchical physical design.
12. A computer-readable medium as recited in claim 11 wherein said physical design includes a top-level physical design.
13. A computer-readable medium as recited in claim 11 wherein said physical design includes a block-level physical design.
14. A computer-readable medium as recited in claim 8 wherein said step by d) includes:
at each location along a boundary between a first block and a second block in which a route path between a source port of said first block and a destination port of said second block crosses said boundary, forming a first pin for said first block and forming a second pin for said second block, wherein said first and second pins are abutted.
15. A method of optimizing a top-level routing for a plurality of ports of a plurality of blocks of a physical design to determine pin assignment, comprising:
a) determining a first plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells;
b) determining whether said plurality of ports includes one or more unused ports;
c) if said plurality of ports includes one or more unused ports, removing said one or more unused ports from a top-level netlist;
d) at a top-level, placing each one of said first plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement;
e) at said top-level, routing said first plurality of ports using a routing wire; and
f) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks.
16. A method as recited in claim 15 wherein said physical design is an abutted-pin hierarchical physical design.
17. A method as recited in claim 16 wherein said physical design includes a top-level physical design.
18. A method as recited in claim 16 wherein said physical design includes a block-level physical design.
19. A method as recited in claim 15 further comprising:
removing one or more excess pins from said plurality of blocks based on criteria.
20. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of optimizing a top-level routing for a plurality of ports of a plurality of blocks of a physical design to determine pin assignment, said method comprising:
a) determining a first plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells;
b) determining whether said plurality of ports includes one or more unused ports;
c) if said plurality of ports includes one or more unused ports, removing said one or more unused ports from a top-level netlist;
d) at a top-level, placing each one of said first plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement;
e) at said top-level, routing said first plurality of ports using a routing wire; and
f) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks.
21. A computer-readable medium as recited in claim 20 wherein said physical design is an abutted-pin hierarchical physical design.
22. A computer-readable medium as recited in claim 21 wherein said physical design includes a top-level physical design.
23. A computer-readable medium as recited in claim 21 wherein said physical design includes a block-level physical design.
24. A computer-readable medium as recited in claim 20 wherein said method further comprises:
removing one or more excess pins from said plurality of blocks based on criteria.
25. A method of optimizing a top-level routing for a plurality of ports of a plurality of blocks of a physical design to determine pin assignment, comprising:
a) determining a first plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells;
b) determining whether said plurality of ports includes a second plurality of first ports of a first block that couple to a second port of a second block;
c) if said plurality of ports includes said second plurality of first ports of said first block that couple to said second port of said second block, removing excess first ports from a top-level netlist based on criteria; and
d) at a top-level, placing each one of said first plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement;
e) at said top level, routing said first plurality of ports using a routing wire; and
f) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks.
26. A method as recited in claim 25 wherein said physical design is an abutted-pin hierarchical physical design.
27. A method as recited in claim 26 wherein said physical design includes a top-level physical design.
28. A method as recited in claim 26 wherein said physical design includes a block-level physical design.
29. A method as recited in claim 25 further comprising:
removing one or more excess pins from said plurality of blocks based on criteria.
30. A method as recited in claim 25 wherein said criteria includes designation of an input port.
31. A method as recited in claim 25 wherein said criteria includes designation of an output port.
32. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of optimizing a top-level routing for a plurality of ports of a plurality of blocks of a physical design to determine pin assignment, said method comprising:
a) determining a first plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells;
b) determining whether said plurality of ports includes a second plurality of first ports of a first block that couple to a second port of a second block;
c) if said plurality of ports includes said second plurality of first ports of said first block that couple to said second port of said second block, removing excess first ports from a top-level netlist based on criteria; and
d) at a top-level, placing each one of said first plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement;
e) at said top-level routing said first plurality of ports using a routing wire; and
f) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks.
33. A computer-readable medium as recited in claim 32 wherein said physical design is an abutted-pin hierarchical physical design.
34. A computer-readable medium as recited in claim 33 wherein said physical design includes a top-level physical design.
35. A computer-readable medium as recited in claim 33 wherein said physical design includes a block-level physical design.
36. A computer-readable medium as recited in claim 32 wherein said method further comprises:
removing one or more excess pins from said plurality of blocks based on criteria.
37. A computer-readable medium as recited in claim 32 wherein said criteria includes designation of an input port.
38. A computer-readable medium as recited in claim 32 wherein said criteria includes designation of an output port.
39. A method of optimizing a top-level routing for a plurality of ports of a plurality of blocks of a physical design to determine pin assignment, comprising:
a) determining a first plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells;
b) determining whether said plurality of ports includes one or more ports that are coupled to a power line;
c) determining whether said plurality of ports includes one or more ports that are coupled to a ground line;
d) if said plurality of ports includes one or more ports that are coupled to said power line, removing said ports that are coupled to said power line from a top-level netlist;
e) if said plurality of ports includes one or more ports that are coupled to said ground line, removing said ports that are coupled to said ground line from said top-level netlist; and
f) at a top-level, placing each one of said first plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement;
g) at said top-level, routing said first plurality of ports using a routing wire; and
h) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks.
40. A method as recited in claim 39 wherein said physical design is an abutted-pin hierarchical physical design.
41. A method as recited in claim 40 wherein said physical design includes a top-level physical design.
42. A method as recited in claim 40 wherein said physical design includes a block-level physical design.
43. A method as recited in claim 39 further comprising:
removing one or more excess pins from said plurality of blocks based on criteria.
44. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of optimizing a top-level routing for a plurality of ports of a plurality of blocks of a physical design to determine pin assignment, comprising:
a) determining a first plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells;
b) determining whether said plurality of ports includes one or more ports that are coupled to a power line;
c) at determining whether said plurality of ports includes one or more ports that are coupled to a ground line;
d) if said plurality of ports includes one or more ports that are coupled to said power line, removing said ports that are coupled to said power line from a top-level netlist;
e) if said plurality of ports includes one or more ports that are coupled to said ground line, removing said ports that are coupled to said ground line from said top-level netlist; and
f) at a top-level, placing each one of said first plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement;
g) at said top-level, routing said first plurality of ports using a routing wire; and
h) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks.
45. A computer-readable medium as recited in claim 44 wherein said physical design is an abutted-pin hierarchical physical design.
46. A computer-readable medium as recited in claim 45 wherein said physical design includes a top-level physical design.
47. A computer-readable medium as recited in claim 45 wherein said physical design includes a block-level physical design.
48. A computer-readable medium as recited in claim 44 wherein said method further comprises:
removing one or more excess pins from said plurality of blocks based on criteria.