Automatic phase lock loop design using geometric programming
View Patent ↗A method is described that involves developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of the PLL at the system level, a lower level expression that describes a characteristic of one the PLL's basic building blocks.
1. A method comprising:
substituting one or more lower level posynomial and/or monomial behavioral expressions into a plurality of higher level posynomial and/or monomial behavioral expressions of a system level circuit description of a phase lock loop said substituting causing a plurality of transistor level posynomial and/or monomial expressions having one or more undefined transistor parameters to be developed;
constructing a geometric problem with the plurality of transistor level posynomial and/or monomial expressions; and
solving the geometric problem to determine the one or more undefined transistor parameters.
2. The method of claim 1 , further comprising creating the system level circuit description.
3. The method of claim 2 , further comprising substituting one or more lower level circuit topologies into a plurality of higher level circuit topologies until a transistor level circuit topology is formed.
4. The method of claim 3 , further comprising combining the transistor level circuit topology with the one or more transistor parameters determined.
5. The method of claim 1 , further comprising retrieving one or more of the lower level posynomial and/or monomial behavioral expressions from a first database.
6. The method of claim 3 , further comprising retrieving one or more of the lower level circuit topologies from a second database.
7. The method of claim 2 , wherein creating the system level circuit description comprises:
receiving one or more system level constraints; and
applying the one or more system level constraints to a plurality of system level posynomial and/or monomial behavioral expressions.
8. The method of claim 7 , further comprising:
creating system level definition information; and
retrieving the plurality of system level posynomial and/or monomial behavioral expressions.
9. The method of claim 7 , further comprising:
receiving system level definition information; and
constructing the plurality of system level posynomial and/or monomial behavioral expressions.
10. The method of claim 7 , further comprising:
creating system level definition information; and
constructing the plurality of system level posynomial and/or monomial behavioral expressions.
11. The method of claim 7 , further comprising:
receiving system level definition information; and
retrieving the plurality of system level posynomial and/or monomial behavioral expressions.
12. The method of claim 7 , further comprising retrieving system level circuit topology information to produce a system level circuit topology.
13. The method of claim 1 , wherein the one or more undefined transistor parameters include an undefined transistor dimension.
14. The method of claim 1 , wherein the circuit system includes a phase lock loop circuit.
15. The method of claim 1 , further comprising:
using the one or more transistor parameters determined to generate a design for the phase lock loop.
16. A machine-readable medium embodying instructions, the instructions, when executed by a processor, causing the processor to perform a method, the method comprising:
substituting one or more lower level posynomial and/or monomial behavioral expressions into a plurality of higher level posynomial and/or monomial behavioral expressions of a system level circuit description of a phase lock loop said substituting causing a plurality of transistor level posynomial and/or monomial expressions having one or more undefined transistor parameters to be developed;
constructing a geometric problem with the plurality of transistor level posynomial and/or monomial expressions; and
solving the geometric problem to determine the one or more undefined transistor parameters.
17. The machine-readable medium in claim 16 , wherein the method further comprises creating the system level circuit description.
18. The machine-readable medium in claim 17 , wherein the method further comprises substituting one or more lower level circuit topologies into a plurality of higher level circuit topologies until a transistor level circuit topology is formed.
19. The machine-readable medium in claim 18 , wherein the method further comprises combining the transistor level circuit topology with the one or more transistor parameters determined.
20. The machine-readable medium in claim 16 , wherein the method further comprises retrieving one or more of the lower level posynomial and/or monomial behavioral expressions from a first database.
21. The machine-readable medium in claim 18 , wherein the method further comprises retrieving one or more of the lower level circuit topologies from a second database.
22. The machine-readable medium in claim 18 , wherein creating the system level circuit description comprises:
receiving one or more system level constraints; and
applying the one or more system level constraints to a plurality of system level posynomial and/or monomial behavioral expressions.
23. The machine-readable medium in claim 22 , wherein the method further comprising:
creating system level definition information; and
retrieving the plurality of system level posynomial and/or monomial behavioral expressions.
24. The machine-readable medium in claim 22 , wherein the method further comprising:
receiving system level definition information; and
retrieving the plurality of system level posynomial and/or monomial behavioral expressions.
25. The machine-readable medium in claim 22 , wherein the method further comprising:
creating system level definition information; and
constructing the plurality of system level posynomial and/or monomial behavioral expressions.
26. The machine-readable medium in claim 22 , wherein the method further comprising:
receiving system level definition information; and
constructing the plurality of system level posynomial and/or monomial behavioral expressions.
27. The machine-readable medium in claim 22 , wherein the method further comprising retrieving system level circuit topology information to produce a system level circuit topology.
28. The machine-readable medium in claim 16 , wherein one or more undefined transistor parameters include an undefined transistor dimension.
29. The machine-readable medium in claim 16 , wherein the circuit system includes a phase lock loop circuit.
30. The machine-readable medium in claim 16 , wherein the method further comprises:
using the one or more transistor parameters determined to generate a design for the phase lock loop.