Patent Assignment
Reel/Frame 028323/0056
Change of Name
Recorded: 2012-06-05
Pages: 6
Assignor
MAGMA DESIGN AUTOMATION, INC.
Executed: 2012-02-22
Assignee
MAGMA DESIGN AUTOMATION LLC
2711 CENTERVILLE RD STE 400, WILMINGTON, DELAWARE, 19808
Covered Properties
(28)
Generalized Theory of Logical Effort for Look-Up Table Based Delay Models
Patent:
6,253,361 →
Application:
09/295,938 →
Automated Design of Parallel Drive Standard Cells
Patent:
6,496,965 →
Application:
09/399,986 →
Method for Providing Convex Piecewise-Linear Expression for Multiple Variable System
Patent:
6,813,590 →
Application:
09/475,734 →
Parser for Signomial and Geometric Programs
Patent:
7,299,459 →
Application:
09/752,541 →
Method and Apparatus for Calculation of Crosstalk Noise in Integrated Circuits
Patent:
7,013,253 →
Application:
09/823,085 →
Optimal Simultaneous Design and Floorplanning of Integrated Circuit
Method and Apparatus for Automatic Analog/Mixed Signal System Design Using Geometric Programming
Method and Apparatus for Routing an Integrated Circuit
Patent:
6,877,148 →
Application:
10/118,673 →
Efficient Layout Strategy for Automated Design Layout Tools
Method and Apparatus for Automatic Layout of Circuit Structures
Patent:
6,789,246 →
Application:
10/119,326 →
Automatic Phase Lock Loop Design Using Geometric Programming
Methodology for Design of Oscillator Delay Stage and Corresponding Applications
Patent:
7,039,885 →
Application:
10/348,723 →
Delay Stage for Oscillator Circuit and Corresponding Applications
Patent:
7,102,449 →
Application:
10/348,822 →
Method and Apparatus for Efficient Semiconductor Process Evaluation
Analog Circuit Power Distribution Circuits and Design Methodologies for Producing Same
Patent:
7,013,436 →
Application:
10/444,602 →
Capacitor Structure and Automated Design Flow for Incorporating Same
Patent:
6,963,122 →
Application:
10/656,793 →
Automatic Phase Lock Loop Design Using Geometric Programming
Circuit Optimization with Posynomial Function F Having an Exponent of a First Design Parameter
Novel Optimization for Circuit Design
Novel Optimization for Circuit Design
Parser for signomial and geometric programs
Application:
11/986,253 →
Publication:
US 2008/0072215
Multi-Threaded Global Routing
Patent:
8,234,614 →
Application:
12/156,963 →
Automated Circuit Design Using Active Set Solving Process
Patent:
8,307,309 →
Application:
12/195,326 →
Structured Placement For Bit Slices
Automated Circuit Design Process for Generation of Stability Constraints for Generically Defined Electronic System with Feedback
Novel Optimization for Circuit Design
Automated Circuit Design Process For Generation of Stability Constraints for Generically Defined Electronic System with Feedback
Application:
61/120,016 →
Structured placement for bit slices
Application:
61/131,158 →
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.