IP Library Granted Patent US 8,307,309
Granted Patent B1
US 8,307,309 · App. 12/195,326 · Granted Nov 6, 2012

Automated circuit design using active set solving process

Assignee: Synopsys, Inc.
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Quick Facts
Patent No.
US 8,307,309
App. No.
12/195,326
Granted
Nov 6, 2012
Kind
B1
Abstract

A method is described that involves identifying a subset of operational scenarios for a circuit being designed. The family of equations are solved for the circuit over the subset and the solving produces numeric values for design parameters of the circuit. The family of equations enhanced with said numeric values are solved over a remainder of the scenarios and none of the remaining scenarios are identified as being infeasible scenarios. A design for the circuit that includes the numeric values is produced.

Claims (51)

1. A method, comprising:

performing the following by processing program code with one or more processors:

identifying a subset of operational scenarios defining environments for a circuit being designed;

concurrently solving a family of equations for said circuit over said subset, said solving

producing numeric values for design parameters of said circuit;

individually solving said family of equations enhanced with said numeric values over a remainder of said scenarios and identifying said remaining scenarios as being feasible scenarios; and,

producing a design for said circuit that includes said numeric values.

2. The method of claim 1 wherein said producing a design includes producing a transistor level netlist for said circuit.

3. The method of claim 1 wherein said scenarios include different combinations of at least one of: manufacturing process corner, temperature and supply voltage.

4. The method of claim 1 wherein said design parameters include unknown and scenario independent dimensions of transistors within said circuit.

5. The method of claim 1 wherein said design parameters include at least one of the following unknown and scenario dependent variables:

an electrical current within said circuit;

a voltage within said circuit.

6. The method of claim 1 wherein said equations are signomial and said solving is performed by a signomial programming problem solver.

7. The method of claim 1 wherein each of said equations are posynomial and said solving is performed by a geometric programming problem solver.

8. A method, comprising:

performing the following by processing program code with one or more processors:

identifying a subset of operational scenarios defining environments for a circuit being designed;

concurrently solving a family of equations for said circuit over said subset, said solving producing numeric values for design parameters of said circuit including scenario dependent unknowns of said subset;

sequentially solving said family of equations enhanced with said numeric values over a remainder of said scenarios and identifying one or more of said remaining scenarios as infeasible scenarios;

adding said infeasible scenarios to said subset and resolving said family of equations to produce second numeric values for said design parameters; and,

solving said family of equations with said second numeric values over a second remainder of said scenarios and producing a design for said circuit that includes said second numeric values.

9. The method of claim 8 wherein said design parameters includes dimensions for transistors within said circuit.

10. The method of claim 9 wherein said producing a design includes producing a transistor level netlist for said circuit.

11. The method of claim 8 wherein said scenarios include different combinations of at least one of: manufacturing process corner, temperature and supply voltage.

12. The method of claim 11 wherein said scenarios include different combinations of at least one of: manufacturing process corner, temperature and supply voltage.

13. The method of claim 8 wherein said design parameters are unknown and scenario independent.

14. The method of claim 13 wherein said unknown and scenario independent variables include dimensions of transistors within said circuit.

15. The method of claim 8 wherein said design parameters include parameters that are unknown and scenario dependent.

16. The method of claim 15 wherein said unknown and scenario dependent variables include at least one of:

an electrical current within said circuit;

a voltage within said circuit.

17. The method of claim 8 wherein said equations are signomial and said solving is performed by a signomial programming problem solver.

18. The method of claim 8 wherein said equations are posynomial and said solving is performed by a geometric programming problem solver.

19. A machine readable storage medium and not a transitory electromagnetic signal having program code stored thereon that when processed by a processing unit causes a method to be performed, said method comprising:

identifying a subset of operational scenarios defining environments for a circuit being designed;

concurrently solving a family of equations for said circuit over said subset, said solving producing numeric values for design parameters of said circuit;

individually solving said family of equations enhanced with said numeric values over a remainder of said scenarios and identifying said remaining scenarios as being feasible scenarios; and,

producing a design for said circuit that includes said numeric values.

20. The machine readable storage medium of claim 19 wherein said design parameters include unknown and scenario independent dimensions of transistors within said circuit.

21. A computing system having a machine readable storage medium and not a transitory electromagnetic signal with program code stored thereon that when executed by said computing system's processing resources cause a method to be performed, said method comprising:

identifying a subset of operational scenarios defining environments for a circuit being designed;

concurrently solving a family of equations for said circuit over said subset, said solving producing numeric values for design parameters of said circuit;

individually solving said family of equations enhanced with said numeric values over a remainder of said scenarios and identifying said remaining scenarios as being feasible scenarios; and,

producing a design for said circuit that includes said numeric values.

22. The computing system of claim 19 wherein said scenarios include different combinations of temperature and supply voltage.

23. The computing system of claim 21 wherein said subset includes seven different scenarios having different combinations of values for corner, temperature, VDD and reference current where said values are respectively chosen from the following options:

A. Corner={Typical-Typical, Slow-Slow, Fast-Fast}

B. Temperature={Nominal, Hot, Cold}

C. V DD ={Nominal, High, Low}

D. Reference Current={Nominal, High, Low}.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 11, 2016
From: WELLS FARGO CAPITAL FINANCE, LLC
To: SYNOPSYS, INC.
Reel/Frame 040607/0632 →
CHANGE OF NAME Recorded Jun 5, 2012
From: MAGMA DESIGN AUTOMATION, INC.
To: MAGMA DESIGN AUTOMATION LLC
Reel/Frame 028323/0056 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2012
From: MAGMA DESIGN AUTOMATION LLC
To: SYNOPSYS, INC.
Reel/Frame 028323/0064 →
SECURITY AGREEMENT Recorded Mar 23, 2010
From: MAGMA DESIGN AUTOMATION, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC
Reel/Frame 024120/0809 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2008
From: DEL MAR HERSHENSON, MARIA; MOHAN, SUNDERARAJAN S.
To: MAGMA DESIGN AUTOMATION, INC.
Reel/Frame 021996/0188 →