Optimization for circuit design
View Patent ↗Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics.
1. A method to design and optimize a circuit having components characterized by one or more design parameters, comprising:
processing program code with a computing system to perform the following:
generating a linear function g 1 comprising a first design parameter and a posynomial function ƒ comprising an exponent of the first design parameter, the linear and posynomial functions for use in performance specifications for the circuit;
providing constraint values for the performance specifications;
generating a convex optimization problem comprising the functions identifying the performance specifications; and
solving the convex optimization problem to produce one or more optimized design parameter values for the circuit.
2. The method of claim 1 wherein the posynomial function ƒ further comprises a second design parameter.
3. The method of claim 1 further comprising generating a second posynomial function ƒ 2 of the one or more of the design parameters.
4. The method of claim 1 wherein the linear function g 1 provides optimized design parameter values for one or more voltage values in the analog circuit.
5. The method of claim 4 wherein the one or more voltage values are calculated using Kirchoff's voltage law.
6. The method of claim 1 wherein design parameters for transistors are selected.
7. The method of claim 6 wherein the transistors comprise Metal-Oxide-Semiconductor (MOS) transistors.
8. The method of claim 7 wherein the design parameters comprise a transistor drain current.
9. The method of claim 1 wherein the design parameters comprise a semiconductor junction capacitance.
10. The method of claim 7 wherein the design parameters comprise any of:
(a) a transistor width (W);
(b) a transistor length (L);
(c) a two-terminal voltage of one of the MOS transistors; and
(d) a two-terminal capacitance of one of the MOS transistors.
11. The method of claim 7 wherein the design parameters comprise a gate-to-source capacitance c gs .
12. The method of claim 7 wherein the design parameters comprise a transconductance g m of a transistor.
13. The method of claim 7 wherein the design parameters comprise an output conductance g ds of a transistor.
14. The method of claim 7 wherein the design parameters comprise one or more parameters of a transistor in a weak inversion region of operation.
15. The method of claim 7 wherein the design parameters comprise one or more parameters of a transistor in a strong inversion region of operation.
16. The method of claim 7 wherein the design parameters comprise one or more parameters of a transistor in a sub-threshold region of operation.
17. The method of claim 7 wherein the design parameters comprise a gate-to-source voltage V gs .
18. The method of claim 6 wherein the transistors comprise Bipolar Junction transistors (BJTs).
19. The method of claim 18 wherein the design parameters comprise a collector-emitter current I ce of a transistor.
20. The method of claim 1 wherein the generating and providing result in the formulation of an optimization problem comprising an objective function ƒ 0 (x 1 ,x 2 ) subject to constraint functions ƒ posynomial on e x 1 and x 2 , and g 1 linear on x 1 , wherein x 1 and x 2 comprise design parameters and wherein ƒ 0 (x 1 ,x 2 ) can take the form any of the constraint functions.
21. The method of claim 20 further comprising the constraint function ƒ 2 posynomial on x 2 .
22. The method of claim 21 wherein the converting the optimization problem into a convex problem comprises:
substituting y 2 =log x 2 into ƒ 0 and ƒ;
defining Previously Presented functions ƒ′=log ƒ(x 1 ,y 2 ) and ƒ 2′ =log ƒ 2 (y 2 ), and
reformulating the convex optimization problem to produce an optimization function ƒ 0 ′ (x 1 , y 2 ) subject to constraint functions ƒ′ convex on x 1 and y 2 , ƒ 2′ convex on y 2 , and g 1 affine on x 1 .
23. The method of claim 20 wherein the solving the convex problem comprises using interior-point methods.
24. A computer readable storage medium comprising program code that when processed by a computer causes a method to design and optimize a circuit having components characterized by one or more design parameters to be performed, comprising:
generating a linear function g 1 comprising a first design parameter and a posynomial function ƒ comprising an exponent of the first design parameter, the linear and posynomial functions for use in performance specifications for the circuit;
providing constraint values for the performance specifications;
generating a convex optimization problem comprising the functions identifying the performance specifications; and
solving the convex optimization problem to produce one or more optimized design parameter values for the circuit.
25. The computer readable storage medium of claim 24 wherein the design parameters comprise a transistor drain current.
26. The computer readable storage medium of claim 24 wherein the design parameters comprise a semiconductor junction capacitance.
27. The computer readable storage medium of claim 24 wherein the design parameters comprise any of:
(a) a transistor width (W);
(b) a transistor length (L);
(c) a two-terminal voltage of an MOS transistor; and
(d) a two-terminal capacitance of an MOS transistor.
28. The computer readable storage medium of claim 24 wherein the design parameters comprise a gate-to-source capacitance c gs .
29. The computer readable storage medium of claim 24 wherein the design parameters comprise a transconductance g m of a transistor.
30. The computer readable storage medium of claim 24 wherein the design parameters comprise an output conductance g ds of a transistor.
31. The computer readable storage medium of claim 24 wherein the design parameters comprise one or more parameters of a transistor in a weak inversion region of operation.
32. The computer readable storage medium of claim 24 wherein the design parameters comprise one or more parameters of a transistor in a strong inversion region of operation.
33. The computer readable storage medium of claim 24 wherein the design parameters comprise one or more parameters of a transistor in a sub-threshold region of operation.
34. The computer readable storage medium of claim 24 wherein the design parameters comprise a gate-to-source voltage V gs .
35. The computer readable storage medium of claim 24 wherein the transistors comprise Bipolar Junction transistors (BJTs).
36. The computer readable storage medium of claim 35 wherein the design parameters comprise a collector-emitter current I ce of a transistor.