Automatic phase lock loop design using geometric programming
View Patent ↗A method is described that involves developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of the PLL at the system level, a lower level expression that describes a characteristic of one the PLL's basic building blocks.
1. A method comprising:
executing software instructions using a processor to develop a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of said PLL at the system level, a lower level expression that describes a characteristic of one said PLL's basic building blocks;
constructing a geometric problem with the lower level expression; and
solving the geometric problem to generate the more detailed description of the phase lock loop system, the more detailed description of the phase lock loop system comprising a transistor-level netlist.
2. The method of claim 1 ,further comprising:
recognizing a variable within the monomial or posynomial expression for one of the functional characteristics of said PLL as having a dependency on the lower level expression.
3. The method of claim 2 , further comprising substituting the lower level expression into the monomial or posynomial equation to replace the variable within the monomial or posynomial expression.
4. A machine-readable medium embodying instructions, the instructions, when executed by a processor, causing the processor to perform operations comprising:
developing a more detailed description of a phase lock loop system by substituting, into a monomial or posynomial equation that is part of a family of monomial and posynomial expressions that describe functional characteristics of said PLL at the system level, a lower level expression that describes a characteristic of one said PLL's basic building blocks;
constructing a geometric problem with the lower level expression; and
solving the geometric problem to generate the more detailed description of the phase lock loop system, the more detailed description of the phase lock loop system comprising a transistor-level netlist.
5. The machine-readable medium in claim 4 , wherein the operations further comprise:
recognizing a variable within the monomial or posynomial expression for one of the functional characteristics of said PLL as having a dependency on the lower level expression.
6. The machine-readable medium in claim 5 , wherein the operations further comprise substituting the lower level expression into the monomial or posynomial equation to replace the variable within the monomial or posynomial expression.