Redundantly tied metal fill for IR-drop and layout density optimization
View Patent ↗An integrated circuit and a method for using metal fill geometries to reduce the voltage drop in power meshes. Metal fill geometries are connected to the power mesh using vias or wires at multiple locations. Metal fill geometries are connected to other floating metal fill geometries using vias or wires at multiple locations. The circuit design introduces maximum redundancy between metal fill geometries and power mesh geometries, but partial redundancy between metal fill geometries and metal fill geometries. In particular, the redundancy in connectivity between metal fill geometries and metal fill geometries is kept minimal to reduce the number of geometries introduced. The high redundancy between metal fill geometries and power mesh geometries and the partial redundancy among metal fill geometries result in a smaller IR-drop by reducing the effective resistance on a power mesh. Hence, the invention use redundancy carefully and advantageously to achieve simultaneous metal density and IR-drop optimization without introducing excessive number of metal fill geometries.
1. A method of tying metal fill geometries in an integrated circuit, comprising steps of:
defining a power mesh structure on a plurality of metal layers on the integrated circuit, wherein the power mesh structure is electrically connected to a plurality of power rails wherein the plurality of power rails are on a layer of the integrated circuit;
adding a plurality of metal fill geometries to portions of the integrated circuit in response to a predetermined metal density requirement;
electrically connecting a first metal fill geometry to the power mesh structure, wherein the first metal fill geometry is redundantly connected with the power mesh structure; and
electrically connecting a second metal fill geometry to the first metal fill geometry, wherein the second metal fill geometry has a partial redundant connection with the first metal fill geometry such that there exists at least one electrical path between the first metal fill geometry and the second metal fill geometry that does not go through a redundant connection.
2. The method of claim 1 , further comprising electrically connecting a third metal fill geometry to the first metal fill geometry.
3. The method of claim 1 , wherein the first metal fill geometry and the second metal fill geometry are in different layers of the integrated circuit.
4. The method of claim 1 , further comprising removing a metal fill geometry not electrically connected with the power mesh structure.
5. The method of claim 1 , wherein the plurality of metal fill geometries are connected to satisfy a predetermined IR-drop requirement.
6. The method of claim 1 , wherein redundant electrical connections are used to electrically connect the first metal fill geometry to the power mesh structure.
7. The method of claim 1 , wherein a metal fill to metal fill interlevel connection satisfies a loop-free test.
8. An integrated circuit comprising:
a power mesh structure on a plurality of layers on the integrated circuit, wherein the power mesh structure is electrically connected to a plurality of power rails wherein the plurality of power rails are on a layer of the integrated circuit;
a plurality of metal fill geometries in empty portions of the integrated circuit to satisfy metal density requirements;
a first metal fill geometry electrically connected to the power mesh structure, wherein the first metal fill geometry is redundantly connected to the power mesh structure; and
a second metal fill geometry electrically connected to the first metal fill geometry, wherein the second metal fill geometry has a partial redundant connection to the first metal fill geometry such that there exists at least one electrical path between the first metal fill geometry and the second metal fill geometry that does not go through a redundant connection.
9. The integrated circuit of claim 8 , further comprising a third metal fill geometry of the plurality of metal fill geometries connected to the first metal fill geometry.
10. The integrated circuit of claim 8 , wherein the first metal fill geometry and the second metal fill geometry are in different layers of the integrated circuit.
11. The integrated circuit of claim 8 , wherein each metal fill geometry is electrically connected to the power mesh structure.
12. The integrated circuit of claim 8 , wherein the IR-drop requirements are satisfied.
13. The integrated circuit of claim 8 , wherein redundant electrical connections are used to electrically connect the first metal fill geometry to the power mesh structure.
14. The integrated circuit of claim 8 , wherein a metal fill to metal fill interlevel connection satisfies a loop-free test.
15. A method of tying metal fill geometries in an integrated circuit, comprising:
defining a power mesh structure on a plurality of metal layers on the integrated circuit, wherein the power mesh structure is electrically connected to a plurality of power rails wherein the plurality of power rails are on a layer of the integrated circuit;
adding a plurality of metal fill geometries to portions of the integrated circuit in response to a predetermined metal density requirement;
electrically connecting a first metal fill geometry to the power mesh structure, wherein the first metal fill geometry is redundantly connected with the power mesh structure; and
electrically connecting a second metal fill geometry to the first metal fill geometry, wherein the second metal fill geometry is partially redundantly connected with the first metal fill geometry; and
removing a metal fill geometry not electrically connected with the power mesh structure.
16. A method of tying metal fill geometries in an integrated circuit, comprising:
defining a power mesh structure on a plurality of metal layers on the integrated circuit, wherein the power mesh structure is electrically connected to a plurality of power rails wherein the plurality of power rails are on a layer of the integrated circuit;
adding a plurality of metal fill geometries to portions of the integrated circuit in response to a predetermined metal density requirement;
electrically connecting a first metal fill geometry to the power mesh structure, wherein the first metal fill geometry is redundantly connected with the power mesh structure; and
electrically connecting a second metal fill geometry to the first metal fill geometry such that a predetermined IR-drop requirement is satisfied, wherein the second metal fill geometry is partially redundantly connected with the first metal fill geometry.
17. The method of claim 16 , further comprising electrically connecting a third metal fill geometry to the first metal fill geometry.
18. The method of claim 16 , wherein the first metal fill geometry and the second metal fill geometry are in different layers of the integrated circuit.
19. A method of tying metal fill geometries in an integrated circuit, comprising:
defining a power mesh structure on a plurality of metal layers on the integrated circuit, wherein the power mesh structure is electrically connected to a plurality of power rails wherein the plurality of power rails are on a layer of the integrated circuit;
adding a plurality of metal fill geometries to portions of the integrated circuit in response to a predetermined metal density requirement;
electrically connecting a first metal fill geometry to the power mesh structure, wherein the first metal fill geometry is redundantly connected with the power mesh structure; and
electrically connecting a second metal fill geometry to the first metal fill geometry, wherein the second metal fill geometry is partially redundantly connected with the first metal fill geometry such that a loop-free test is satisfied.
20. An integrated circuit comprising:
a power mesh structure on a plurality of layers on the integrated circuit, wherein the power mesh structure is electrically connected to a plurality of power rails wherein the plurality of power rails are on a layer of the integrated circuit;
a plurality of metal fill geometries in empty portions of the integrated circuit to satisfy metal density requirements;
a first metal fill geometry electrically connected to the power mesh structure, wherein the first metal fill geometry is redundantly connected to the power mesh structure; and
a second metal fill geometry electrically connected to the first metal fill geometry such that a predetermined IR-drop requirement is satisfied, wherein the second metal fill geometry is partially redundantly connected to the first metal fill geometry.
21. The integrated circuit of claim 20 further comprising a third metal fill geometry of the plurality of metal fill geometries connected to the first metal fill geometry.
22. The integrated circuit of claim 20 , wherein the first metal fill geometry and the second metal fill geometry are in different layers of the integrated circuit.
23. An integrated circuit comprising:
a power mesh structure on a plurality of layers on the integrated circuit, wherein the power mesh structure is electrically connected to a plurality of power rails wherein the plurality of power rails are on a layer of the integrated circuit;
a plurality of metal fill geometries in empty portions of the integrated circuit to satisfy metal density requirements;
a first metal fill geometry electrically connected to the power mesh structure, wherein the first metal fill geometry is redundantly connected to the power mesh structure; and
a second metal fill geometry electrically connected to the first metal fill geometry, wherein the second metal fill geometry is partially redundantly connected to the first metal fill geometry, such that a loop-free test is satisfied.