IP Library Assignment 029161/0846
Patent Assignment
Reel/Frame 029161/0846

Nunc Pro Tunc Assignment

Recorded: 2012-10-19 Pages: 4
Assignor
MAGMA DESIGN AUTOMATION LLC
Executed: 2012-10-19
Assignee
SYNOPSYS, INC.
700 EAST MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties (30)
A Method of Automating the Manipulation and Display of Sets of Wafer Yield Data Using a User Interface Smart Macro.
Patent: 6,088,712 →
Application: 08/994,996 →
Method and System for Creating Electronic Circuitry
Patent: 6,327,557 →
Application: 09/090,457 →
Ic Test Software System for Mapping Logical Functional Test Data of Logic Integrated Circuits to Physical Representation
Patent: 6,185,707 →
Application: 09/192,164 →
Method and System for Automatically Generating Low Level Program Commands as Dependency Graphs from High Level Physical Design Stages
Patent: 6,574,788 →
Application: 09/712,418 →
Method and System for Implementing a User Interface for Performing Physical Design Operations on an Integrated Circuit Netlist
Patent: 6,557,153 →
Application: 09/714,296 →
Apparatus for Optimized Constraint Characterization with Degradation Options and Associated Methods
Patent: 6,584,598 →
Application: 09/904,463 →
Publication: US 2002/0144214
Method and System for Implementing a Graphical User Interface for Depicting Loose Fly Line Interconnections Between Multiple Blocks of an Integrated Circuit Netlist
Patent: 6,553,554 →
Application: 09/908,957 →
Method and System for Implementing a Graphical User Interface for Defining and Linking Multiple Attach Points for Multiple Blocks of an Integrated Circuit Netlist
Patent: 6,564,363 →
Application: 09/909,050 →
Method and System for Maintaining Element Abstracts of an Integrated Circuit Netlist Using a Master Library File and Modifiable Master Library File
Patent: 6,564,364 →
Application: 09/909,354 →
System and Method for Limiting Increase in Capacitance Due to Dummy Metal Fills Utilized for Improving Planar Profile Uniformity
Patent: 6,751,785 →
Application: 10/097,978 →
Method of Customizing and Using Maps in Generating the Padring Layout Design
Patent: 6,734,046 →
Application: 10/264,679 →
Method of Generating the Padring Layout Design Using Automation
Patent: 6,823,501 →
Application: 10/264,680 →
Method of Optimizing Placement and Routing of Edge Logic in Padring Layout Design
Patent: 7,117,469 →
Application: 10/264,691 →
Design-Manufacturing Interface via a Unified Model
Patent: 7,155,689 →
Application: 10/680,592 →
Publication: US 2005/0076316
Reduction of Cross-Talk Noise in Vlsi Circuits
Patent: 7,058,907 →
Application: 10/776,402 →
Publication: US 2004/0205678
Modeling Interconnected Propagation Delay for an Integrated Circuit Design
Patent: 7,213,221 →
Application: 10/827,791 →
Floorplanning a Hierarchical Physical Design to Improve Placement and Routing
Patent: 7,155,693 →
Application: 10/831,700 →
Creating a Power Distribution Arrangement with Tapered Metal Wires for a Physical Design
Patent: 7,185,305 →
Application: 10/855,539 →
Optimizing Locations of Pins for Blocks in a Hierarchical Physical Design by Using Physical Design Information of a Prior Hierarchical Physical Design
Patent: 7,114,142 →
Application: 10/855,667 →
Flow Definition Language for Designing Integrated Circuit Implementation Flows
Patent: 7,353,488 →
Application: 10/856,268 →
Asynchronous Control of Memory Self Test
Patent: 7,203,873 →
Application: 10/861,247 →
Redundantly Tied Metal Fill for Ir-Drop and Layout Density Optimization
Patent: 7,240,314 →
Application: 10/861,812 →
Parametric Timing Analysis
Patent: 7,346,874 →
Application: 11/048,287 →
Lithographically Optimized Placement Tool
Patent: 7,434,188 →
Application: 11/372,557 →
Aggregate Sensitivity for Statistical Static Timing Analysis
Patent: 7,458,049 →
Application: 11/451,905 →
Signal Flow Driven Circuit Analysis and Partitioning Technique
Patent: 7,448,003 →
Application: 11/452,542 →
Publication: US 2007/0006103
Parametric Timing Analysis
Patent: 7,970,590 →
Application: 12/035,898 →
Method for Repeated Block Timing Analysis
Patent: 7,971,168 →
Application: 12/128,919 →
Method for Repeated Block Modification for Chip Routing
Patent: 8,407,650 →
Application: 12/129,916 →
Dynamic Push for Topological Routing of Semiconductor Packages
Patent: 8,006,216 →
Application: 12/134,849 →
Related Assignments (3)
Other recorded transfers of the patents in this record — the chain of ownership.
Release of Security Interest Nov 11, 2016
From: WELLS FARGO CAPITAL FINANCE, LLC
To: SYNOPSYS, INC.
Reel/Frame 040607/0632 →
Change of Name Sep 2, 2020
From: MAGMA DESIGN AUTOMATION, INC.
To: MAGMA DESIGN AUTOMATION LLC
Reel/Frame 053669/0442 →
Change of Name Sep 8, 2020
From: MAGMA DESIGN AUTOMATION, INC.
To: MAGMA DESIGN AUTOMATION LLC
Reel/Frame 053727/0935 →