Optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design
View Patent ↗Method of optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design is provided and described. In one embodiment, a method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit includes retrieving physical design information from a prior physical design of a prior integrated circuit. The physical design information includes a routing congestion profile. Continuing, a router is provided a plurality of constraints based on the routing congestion profile. Then, the router is used to perform a top-level route for generating locations of pins for each block. Each pin of the block is created at a location where a global route enters the block or a location where a global route exits the block.
1. A method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit, said method comprising:
retrieving physical design information from a prior physical design of a prior integrated circuit, wherein said physical design information includes a routing congestion profile;
providing to a router a plurality of constraints based on said routing congestion profile; and
using said router to perform a top-level route for generating locations of pins for each block, wherein each pin of said block is created at one of a location where a global route enters said block and a location where a global route exits said block.
2. The method as recited in claim 1 wherein said physical design is a hierarchical physical design.
3. The method as recited in claim 2 wherein said hierarchical physical design has a top-level and a block-level.
4. The method as recited in claim 2 wherein said hierarchical physical design is an abutted-pin hierarchical physical design.
5. The method as recited in claim 1 wherein said physical design information includes location of obstructions.
6. The method as recited in claim 5 further comprising providing to said router a plurality of second constraints based on said location of said obstructions.
7. The method as recited in claim 6 further comprising using said router to perform said top-level route for generating locations of pins for each block based on said second constraints.
8. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit, said method comprising:
retrieving physical design information from a prior physical design of a prior integrated circuit, wherein said physical design information includes a routing congestion profile;
providing to a router a plurality of constraints based on said routing congestion profile; and
using said router to perform a top-level route for generating locations of pins for each block, wherein each pin of said block is created at one of a location where a global route enters said block and a location where a global route exits said block.
9. The computer-readable medium as recited in claim 8 wherein said physical design is a hierarchical physical design.
10. The computer-readable medium as recited in claim 9 wherein said hierarchical physical design has a top-level and a block-level.
11. The computer-readable medium as recited in claim 9 wherein said hierarchical physical design is an abutted-pin hierarchical physical design.
12. The computer-readable medium as recited in claim 8 wherein said physical design information includes location of obstructions.
13. The computer-readable medium as recited in claim 12 wherein said method further comprises providing to said router a plurality of second constraints based on said location of said obstructions.
14. The computer-readable medium as recited in claim 13 wherein said method further comprises using said router to perform said top-level route for generating locations of pins for each block based on said second constraints.
15. A computer system comprising:
a processor coupled to a bus; and
a memory device couples to said bus, wherein said memory device includes computer-executable instructions stored therein for performing a method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit, said method comprising:
retrieving physical design information from a prior physical design of a prior integrated circuit, wherein said physical design information includes a routing congestion profile;
providing to a router a plurality of constraints based on said routing congestion profile; and
using said router to perform a top-level route for generating locations of pins for each block, wherein each pin of said block is created at one of a location where a global route enters said block and a location where a global route exits said block.
16. The computer system as recited in claim 15 wherein said physical design is a hierarchical physical design.
17. The computer system as recited in claim 16 wherein said hierarchical physical design has a top-level and a block-level.
18. The computer system as recited in claim 16 wherein said hierarchical physical design is an abutted-pin hierarchical physical design.
19. The computer system as recited in claim 15 wherein said physical design information includes location of obstructions.
20. The computer system as recited in claim 19 wherein said method further comprises providing to said router a plurality of second constraints based on said location of said obstructions.
21. The computer system as recited in claim 20 wherein said method further comprises using said router to perform said top-level route for generating locations of pins for each block based on said second constraints.