Method for optimized automatic clock gating
View Patent ↗A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
1. A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the method comprising:
identifying, with one or more processors associated with one or more computer systems, a plurality of blocks in the synthesized netlist as idle candidate blocks;
determining, for each idle candidate block, a disable candidate function with the one or more processors associated with one or more computer systems which causes a corresponding sequential element in the idle candidate block to be in an idle state;
generating, with the one or more processors associated with one or more computer systems, a bipartite graph comprising a first set, a second set, and a plurality of edges, the first set including each of the disable candidate functions, the second set including each of the corresponding sequential elements; and
selecting, with the one or more processors associated with one or more computer systems, a subset of the disable candidate functions to be implemented with clock gates in a clock gating structure optimized for power savings, the selected subset enabling an optimal power savings in the IC design.
2. The power optimization method of claim 1 , wherein each edge of the bipartite graph connects a first disable candidate function of the first set to a corresponding first sequential element of the second set.
3. The power optimization method of claim 1 , further comprising:
identifying one or more cliques using the bipartite graph, wherein each clique is a new disable candidate function.
4. The power optimization method of claim 3 , wherein one or more of the new disable candidate functions is a logical combination of two or more disable candidate function.
5. The power optimization method of claim 3 , further comprising:
analyzing each of the disable candidate functions and the new disable candidate functions, wherein the selection is made based on the analysis.
6. The power optimization method of claim 5 , further comprising:
estimating a power savings value for each of the disable candidate functions and the new disable candidate functions, the power savings value based on power consumption by the corresponding sequential element.
7. The power optimization method of claim 1 , further comprising:
generating a matrix representation of the bipartite graph, the matrix representing a logical function of one or more of the disable candidate functions; and
analyzing each of the disable candidate functions using the matrix.
8. The power optimization method of claim 7 , further comprising:
estimating a power savings value for each of the disable candidate functions represented in the matrix.
9. The power optimization method of claim 8 , further comprising:
selecting a candidate disable function with the greatest power savings value.
10. A computer program product stored on a non-transitory computer-readable medium and executable by one or more processors associated with one or more computer systems for deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the computer program product comprising:
code for identifying a plurality of blocks in the synthesized netlist as idle candidate blocks;
code for determining, for each idle candidate block, a disable candidate function which causes a corresponding sequential element in the idle candidate block to be in an idle state;
code for generating a bipartite graph comprising a first set, a second set, and a plurality of edges, the first set including each of the disable candidate functions, the second set including each of the corresponding sequential elements; and
code for selecting a subset of the disable candidate functions to be implemented with clock gates in a clock gating structure optimized for power savings, the selected subset enabling an optimal power savings in the IC design.
11. The computer program product of claim 10 , wherein each edge of the bipartite graph connects a first disable candidate function of the first set to a corresponding first sequential element of the second set.
12. The computer program product of claim 10 , further comprising:
code for identifying one or more cliques using the bipartite graph, wherein each clique is a new disable candidate function.
13. The computer program product of claim 12 , wherein one or more of the new disable candidate functions is a logical combination of two or more disable candidate function.
14. The computer program product of claim 12 , further comprising:
code for analyzing each of the disable candidate functions and the new disable candidate functions, wherein the selection is made based on the analysis.
15. The computer program product of claim 14 , further comprising:
code for estimating a power savings value for each of the disable candidate functions and the new disable candidate functions, the power savings value based on power consumption by the corresponding sequential element.
16. The computer program product of claim 10 , further comprising:
code for generating a matrix representation of the bipartite graph, the matrix representing a logical function of one or more of the disable candidate functions; and
code for analyzing each of the disable candidate functions using the matrix.
17. The computer program product of claim 16 , further comprising:
code for estimating a power savings value for each of the disable candidate functions represented in the matrix.
18. The computer program product of claim 17 , further comprising:
code for selecting a candidate disable function with the greatest power savings value.
19. A system for deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the system comprising:
a processor; and
a memory coupled to the processor, the memory configured to store a plurality of code modules which when executed by the processor cause the processor to:
identify a plurality of blocks in the synthesized netlist as idle candidate blocks;
determine, for each idle candidate block, a disable candidate function which causes a corresponding sequential element in the idle candidate block to be in an idle state;
generate a bipartite graph comprising a first set, a second set, and a plurality of edges, the first set including each of the disable candidate functions, the second set including each of the corresponding sequential elements; and
select a subset of the disable candidate functions to be implemented with clock gates in a clock gating structure optimized for power savings, the selected subset enabling an optimal power savings in the IC design.
20. The system of claim 19 , wherein each edge of the bipartite graph connections a first disable candidate function of the first set to a corresponding first sequential element of the second set.