IP Library › Assignment 040498/0586
Patent Assignment
Reel/Frame 040498/0586

Change of Name

Recorded: 2016-10-26 Pages: 6
Assignor
MAGMA DESIGN AUTOMATION, INC.
Executed: 2012-02-22
Assignee
MAGMA DESIGN AUTOMATION LLC
2711 CENTERVILLE ROAD, SUITE 400, WILMINGTON, DELAWARE, 19808
Covered Properties (21)
Method for Automatic Clock Gating to Save Power
Patent: 7,930,673 →
Application: 12/128,554 →
Publication: US 2008/0301593
Method for Optimized Automatic Clock Gating
Patent: 7,882,461 →
Application: 12/128,574 →
Publication: US 2008/0301594
Timing Analysis Using Statistical on-Chip Variation
Patent: 7,992,114 →
Application: 12/135,031 →
Method for Multi-Cycle Path and False Path Clock Gating
Patent: 7,958,476 →
Application: 12/170,354 →
Clock Gating by Usage of Implied Constants
Patent: 7,710,156 →
Application: 12/343,249 →
Selection of Optimal Clock Gating Elements
Patent: 7,884,649 →
Application: 12/395,268 →
Failure Analysis Using Design Rules
Patent: 8,775,979 →
Application: 12/985,788 →
Publication: US 2011/0191725
Multi-Level Clock Gating Circuitry Transformation
Patent: 8,434,047 →
Application: 13/013,024 →
Signal Tracing Through Boards and Chips
Patent: 8,255,865 →
Application: 13/016,076 →
Publication: US 2011/0191742
Statistical on-Chip Variation Timing Analysis
Patent: 8,307,317 →
Application: 13/195,582 →
Publication: US 2011/0289465
Generation of Independent Logical and Physical Hierarchy
Patent: 8,549,461 →
Application: 13/314,253 →
Publication: US 2012/0151431
Routing Analysis with Double Pattern Lithography
Patent: 8,856,697 →
Application: 13/400,411 →
Publication: US 2012/0216157
Calculation of Integrated Circuit Timing Delay Using Frequency Domain
Patent: 8,504,956 →
Application: 13/460,814 →
Failure Analysis Using Design Rules
Application: 61/299,952 →
Signal Tracing Through Boards and Chips
Application: 61/300,662 →
Generation of Independent Logical and Physical Hierarchy
Application: 61/421,259 →
Routing Analysis with Double Pattern Lithography
Application: 61/446,019 →
Double Pattern Lithography Routing
Application: 61/477,768 →
Automated Inline Defect Characterization
Application: 61/503,289 →
Parasitic Extraction for Semiconductors
Application: 61/544,311 →
Equation Based Transient Circuit Optimization
Application: 61/576,208 →
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Mar 30, 2011
From: HUIJBREGTS, EDUARD PETRUS; DEY, AVIJIT
To: MAGMA DESIGN AUTOMATION, INC.
Reel/Frame 026051/0174 →
Assignment of Assignor's Interest May 4, 2012
From: SHEBAITA, AHMED MAMDOUH
To: MAGMA DESIGN AUTOMATION, INC.
Reel/Frame 028158/0257 →
Nunc Pro Tunc Assignment May 25, 2012
From: MAGMA DESIGN AUTOMATION LLC
To: SYNOPSYS, INC.
Reel/Frame 028269/0807 →
Release of Security Interest Nov 11, 2016
From: WELLS FARGO CAPITAL FINANCE, LLC
To: SYNOPSYS, INC.
Reel/Frame 040607/0632 →