Clock gating by usage of implied constants
View Patent ↗A circuit Θ is coupled to an individual node N in , in a circuit for which repeated logical values of that individual node can be identified as having a set of flip-flops F j dependent thereon, with the effect that if the individual node N in remains unchanged for one or more clock cycles, the set of dependent flip-flops F j can be disabled for the second and succeeding clock cycles. The circuit Θ conditionally generates a clock-enabling signal N out in response thereto. One such circuit Θ conditionally includes a logical controller, whose output is coupled using a fan-out node to both an input to a state machine and a fan-in logic circuit (such as an AND gate). The flip-flop is clocked normally; its output is coupled to that same fan-in logic circuit, whose output N out is coupled to the set of dependent flip-flops F j .
1. Apparatus including
at least one node, in a circuit for which repeated logical values of that node can be identified as having a set of flip-flops dependent thereon, with the effect that if that node remains unchanged for one or more clock cycles, at least a portion of that set of dependent flip-flops can be disabled for at least the second of those clock cycles;
a circuit coupled to that node and to that set of flip-flops, that circuit conditionally generating, in response to that node, a signal in response to which at least that portion of that set of flip-flops can be conditionally enabled.
2. Apparatus as in claim 1 ,
wherein that circuit includes
a fan-out node;
a device maintaining state for at least one clock cycle; and
a logic circuit coupled to that fan-out node and to an output of that device.
3. Apparatus as in claim 2 ,
wherein that circuit includes
a logical controller, responsive to whether that node should remain unchanged in response to a selected set of logical values, an output of that logical controller being coupled to that fan-out node.
4. Apparatus as in claim 1 , including
a delay element coupled to an output of that circuit, and to a second set of flip-flops, that delay element generating, in response to that circuit, a signal in response to which at least a portion of that second set of flip-flops can be conditionally enabled.
5. A method, including steps of
detecting at a node, repeated logical values of that node, for which a set of flip-flops are dependent thereon, such that if that node remains unchanged for one or more clock cycles, at least a portion of that set of dependent flip-flops can be disabled for at least the second of those clock cycles; and
generating, in response to that node, a signal in response to which at least that portion of that set of flip-flops can be conditionally enabled.
6. A method as in claim 5 ,
wherein those steps of detecting include steps of maintaining state for at least one clock cycle.
7. A method as in claim 6 ,
wherein those steps of detecting include steps of operating a logic circuit, an output of that logic circuit being responsive to whether that node remains unchanged in response to a selected set of logical values.
8. A method as in claim 5 , including steps of,
in response to those steps of generating a signal, delaying that signal, wherein those steps of delaying include steps of generating a signal in response to which a second set of flip-flops can be conditionally enabled.