Selection of optimal clock gating elements
View Patent ↗Techniques in which an optimal set of clock gating elements is determined for a selected circuit design. Those clock gating elements are coupled to selected flip-flops, with the effect that those selected flip-flops will consume less dynamic power during operation of the logic circuit. The selected set of clock gating elements provides an optimal savings in overall power consumption after modification of that selected circuit design.
1. A method, including steps of:
identifying information sufficient to describe a set of clock gating elements for a set of circuit elements; and
determining a set of transformations to apply to those circuit elements, with the effect that those clock gating elements are applied to those circuit elements with substantially optimal power reduction for that set of circuit elements, wherein
that step of determining includes steps of:
transforming that information into a data structure having properties of identifying those circuit elements which are responsive to those clock gating elements; and
identifying those clock gating elements to which those circuit elements are responsive, wherein
that step of identifying includes steps of:
identifying a first clock gating element with substantially the best power reduction for that set of circuit elements; and
identifying a second clock gating element with substantially the best gain increase when combined with that first clock gating element; and
in response to those steps of identifying, combining a first data structure associated with that first clock gating element with a second data structure associated with that second clock gating element.
2. A method as in claim 1 , including steps of providing a data structure responsive to a substantial intersection of that first data structure associated with that first clock gating element and that second data structure associated with that second clock gating element.
3. A method as in claim 1 , including steps of removing one or more data structures responsive to that first clock gating element with that substantially best power reduction.
4. A method as in claim 1 , wherein that substantially best gain increase is responsive to at least one of the following:
a combined power reduction for that first clock gating element and that second clock gating element, and
a power reduction for those clock gating elements other than that first clock gating element.
5. A method as in claim 1 , wherein that substantially best power reduction is responsive to a multi-element cost function.
6. A method as in claim 1 , wherein that substantially best power reduction is responsive to at least two of the following:
an approximate probability, or proxy thereof, for a number of transitions saved by that first clock gating element;
an approximate sum, or proxy thereof, for a number of redundant pins that can be removed responsive to that first clock gating element; and
that approximate sum, or proxy thereof, for that number of transitions that are added responsive to that first clock gating element.
7. A method in claim 1 , wherein those steps of identifying that second clock gating element include steps of examining one or more clock gating elements with substantially non-null intersection with that first clock gating element.
8. A method as in claim 1 , wherein that data structure includes:
one or more substructures identifying those circuit elements responsive to those clock gating elements, and
one or more substructures identifying those clock gating elements to which those circuit elements are responsive.
9. A method as in claim 1 , wherein that data structure is capable of being substantially addressable as a matrix, wherein
substantially each of those circuit elements is identified with one of:
a row or column, and wherein
substantially each of those clock gating elements is identified with one of:
a column or row.