Statistical on-chip variation timing analysis
View Patent ↗A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results.
1. A method comprising:
receiving, at one or more processors associated with one or more computer systems, a timing requirement for a timing path in a chip design;
estimating a first timing effect on the timing path that accounts for a random variation occurring independent of location within the chip design;
estimating a second timing effect on the timing path that accounts for a systematic variation within the chip design wherein one or more of the first and the second timing effect is a function of interconnect wiring; and
selecting a margin for the chip design that satisfies the timing requirement after adjusting the timing path for the first timing effect and the second timing effect, wherein estimating the second timing effect includes applying a correlation to a spatial partitioning of the chip design.
2. The method of claim 1 wherein the interconnect wiring connects transistors for the timing path in the chip design.
3. The method of claim 2 wherein the interconnect wiring is within one or more cells in the chip design.
4. The method of claim 1 wherein the estimating of one or more of the first timing effect and the estimating of the second timing effect includes capacitance variation for the interconnect wiring.
5. The method of claim 4 wherein the estimating of one or more of the first timing effect and the estimating of the second timing effect includes resistance variation for the interconnect wiring.
6. The method of claim 1 wherein the estimating of one or more of the first timing effect and the second timing effect includes crosstalk for the interconnect wiring.
7. The method of claim 1 wherein the spatial partitioning includes a plurality of bins, the correlation correlating a variation of a first of the plurality of bins with a variation of a second of the plurality of bins.
8. The method of claim 7 wherein the correlation is a function of distance between the first and the second of the plurality of bins along a power mesh of the chip design.
9. The method of claim 8 wherein the timing path includes a plurality of path delays, each one of the plurality of path delays including at least one cell delay and at least one wire delay.
10. The method of claim 9 wherein estimating the second timing effect includes:
creating a spatial grid for the chip design; and
creating a correlation matrix for the spatial grid that asserts a positive correlation and a correlation distance for regions of the spatial grid that follow the power mesh of the chip design.
11. The method of claim 1 wherein estimating the second timing effect includes evaluating one or more spatial characteristics of a power drop across a power grid of the chip design.
12. The method of claim 1 wherein estimating the first timing effect includes applying statistical static timing analysis to a path delay calculation for the timing path.
13. The method of claim 1 wherein estimating the first timing effect includes applying a formula for one or more cells within the chip design that do not have a statistical library available.
14. The method of claim 1 wherein estimating at least one of the first timing effect and the second timing effect includes conditionally applying a statistical library for a cell of the chip design if the statistical library is available.
15. The method of claim 1 wherein estimating at least one of the first timing effect and the second timing effect includes generating a distribution of possible values for the timing path.
16. The method of claim 1 wherein the systematic variation includes an IR drop across a chip fabricated according to the chip design.
17. The method of claim 1 wherein the timing path includes at least one of a setup time and a hold time.
18. The method of claim 1 further comprising applying the margin to an on-chip variation analysis of the chip design in order to verify timing, thereby providing a verified chip design, and fabricating a chip from the verified chip design.
19. A computer program product comprising computer executable code embodied in a non-transitory computer-readable storage medium that, when executing on one or more computing devices, performs the steps of:
receiving a timing requirement for a timing path in a chip design;
estimating a first timing effect on the timing path that accounts for a random variation occurring independent of location within the chip design;
estimating a second timing effect on the timing path that accounts for a systematic variation within the chip design wherein one or more of the first and the second timing effect is a function of interconnect wiring; and
selecting a margin for the chip design that satisfies the timing requirement after adjusting the timing path for the first timing effect and the second timing effect, wherein estimating the second timing effect includes applying a correlation to a spatial partitioning of the chip design.
20. A system comprising:
a processor; and
a non-transitory computer-readable memory, the memory storing a computer program executable by the processor to perform the steps of:
receiving, at one or more processors associated with one or more computer systems, a timing requirement for a timing path in a chip design;
estimating a first timing effect on the timing path that accounts for a random variation occurring independent of location within the chip design;
estimating a second timing effect on the timing path that accounts for a systematic variation within the chip design wherein one or more of the first and the second timing effect is a function of interconnect wiring; and
selecting a margin for the chip design that satisfies the timing requirement after adjusting the timing path for the first timing effect and the second timing effect, wherein estimating the second timing effect includes applying a correlation to a spatial partitioning of the chip design.
21. The system of claim 20 wherein the estimating of one or more of the first timing effect and the estimating of the second timing effect includes capacitance variation for the interconnect wiring.
22. The system of claim 21 wherein the estimating of one or more of the first timing effect and the estimating of the second timing effect includes resistance variation for the interconnect wiring.
23. The system of claim 20 wherein the estimating of one or more of the first timing effect and the second timing effect includes crosstalk for the interconnect wiring.
24. The system of claim 20 wherein the spatial partitioning includes a plurality of bins, the correlation correlating a variation of a first of the plurality of bins with a variation of a second of the plurality of bins.
25. The system of claim 24 wherein the correlation is a function of distance between the first and the second of the plurality of bins along a power mesh of the chip design.
26. The system of claim 20 wherein estimating the first timing effect includes applying a formula for one or more cells within the chip design that do not have a statistical library available.
27. The system of claim 20 further comprising the computer program executable by the processor to perform the steps of applying the margin to an on-chip variation analysis of the chip design in order to verify timing, thereby providing a verified chip design.
28. The computer program product of claim 19 wherein the estimating of one or more of the first timing effect and the estimating of the second timing effect includes capacitance variation for the interconnect wiring.
29. The computer program product of claim 28 wherein the estimating of one or more of the first timing effect and the estimating of the second timing effect includes resistance variation for the interconnect wiring.
30. The computer program product of claim 19 wherein the estimating of one or more of the first timing effect and the second timing effect includes crosstalk for the interconnect wiring.
31. The computer program product of claim 19 wherein the spatial partitioning includes a plurality of bins, the correlation correlating a variation of a first of the plurality of bins with a variation of a second of the plurality of bins.
32. The computer program product of claim 31 wherein the correlation is a function of distance between the first and the second of the plurality of bins along a power mesh of the chip design.
33. The computer program product of claim 19 wherein estimating the first timing effect includes applying a formula for one or more cells within the chip design that do not have a statistical library available.
34. The computer program product of claim 19 further comprising computer executable code that, when executing on one or more computing devices, performs the steps of the computer program executable by the one or more computing devices to perform the steps of applying the margin to an on-chip variation analysis of the chip design in order to verify timing, thereby providing a verified chip design.