Method of vector generation for estimating performance of integrated circuit designs
View Patent ↗A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. Vectors are generated to estimate integrated circuit performance. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.
1. A method of estimating the performance of an integrated circuit design comprising:
providing a user-specified clock net input;
identifying strongly coupled components coupled to the user-specified clock net input;
determining whether an output of a strongly coupled component is a positive unate or a negative unate; and
marking the output as a part of a clock net.
2. The method of claim 1 wherein the output is a positive unate when switching the user-specified clock net input from low to high, the output is unchanged or changes from low to high.
3. The method of claim 1 wherein the output is a negative unate when switching the user-specified clock net input from low to high, the output is unchanged or changes from high to low.