Granted Patent
Utility
US 6,518,202
· Confirmation No. 1404
METHOD FOR FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-01-03 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-01-03 | SPEC |
Specification | 82 | View | |
| 2001-01-03 | CLM |
Claims | 4 | View | |
| 2001-01-03 | ABST |
Abstract | 1 | View | |
| 2001-01-03 | DRW |
Drawings-only black and white line drawings | 21 | View | |
| 2001-01-03 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Attorneys & Agents of Record
Classification
USPC
438/773
H10P10/00
H10D64/0134
H10D84/0181
H10D84/0167
H10D84/017
H10D84/038
H10D64/693
H10D64/514
H10P14/6322
H10P72/0456
H10P72/0434
H10P72/0472
H10P14/6309
H10D64/01342
H10D64/01344
H10P72/0454
H10P70/15
H10P72/0471
H10D64/01346
H10P14/69215
Y10S148/023
Y10S148/116
Y10S438/935
Prosecution
- Examiner
- KILDAY, LISA A
- Art Unit
- 2829
- Customer No.
- 20457
- Docket No.
- 501.37465VX4
- Confirmation No.
- 1404
Foreign Priority
9-50781
·
1997-03-05
·
JAPAN
Publication
- Pub. No.
- US20010009813A1
- Pub. Date
- 2001-07-26
Patent Term Adjustment
-104days
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Quick Facts
- Patent No.
- US 6,518,202
- App. No.
- 09/752,737
- Filed
- 2001-01-03
- Granted
- 2003-02-11
- Pub. No.
- US20010009813A1
- Examiner
- KILDAY, LISA A
- Art Unit
- 2829
- PTA
- -104 days
External Links