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App. No. 09/768,693 · Confirmation No. 3717

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME

Inventor: Hiroshi Yamamoto
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362 View Patent ↗ View Publication ↗
⬇ PDF
 Code Description Pages PDF
2001-01-24 TRNA Transmittal of New Application 2 View
2001-01-24 SPEC Specification 15 View
2001-01-24 CLM Claims 3 View
2001-01-24 ABST Abstract 1 View
2001-01-24 DRW Drawings-only black and white line drawings 12 View
2001-01-24 OATH Oath or Declaration filed 1 View
2001-01-24 TRNA Transmittal of New Application 2 View
2001-01-24 SPEC Specification 15 View
2001-01-24 CLM Claims 3 View
2001-01-24 ABST Abstract 1 View
2001-01-24 DRW Drawings-only black and white line drawings 12 View
2001-01-24 OATH Oath or Declaration filed 1 View
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Quick Facts
App. No.
09/768,693
Filed
2001-01-24
Granted
2003-04-01
Pub. No.
US20010009381A1
Examiner
TAN, VIBOL
Art Unit
2819
PTA
-120 days