IP Library Granted Patent US 7,105,405
Granted Patent B2
US 7,105,405 · App. 09/770,540 · Granted Sep 12, 2006

Rugged metal electrodes for metal-insulator-metal capacitors

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,105,405
App. No.
09/770,540
Granted
Sep 12, 2006
Kind
B2
Abstract

Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The resulting metal structures are advantageous for high-density DRAM applications since they have good conductivity, enhanced surface area and are compatible with capacitor dielectric materials having high dielectric constant.

Claims (12)

1. A process for fabricating a metal-insulator-metal capacitor on a semiconductor wafer comprising the steps of:

forming a silicon electrode structure on the semiconductor wafer;

making the silicon electrode structure rugged; and

after making the silicon electrode rugged, replacing the silicon in the rugged silicon electrode structure with a metal, thereby forming a rugged metal electrode.

2. The process of claim 1 , further comprising covering the rugged metal electrode with a dielectric layer having a high dielectric constant.

3. The process of claim 2 , further comprising covering the dielectric layer with a metal layer.

4. The process of claim 1 , wherein the step of replacing the silicon in the silicon electrode structure comprises forming a boundary layer on the silicon electrode structure, exposing the silicon electrode structure to a refractory metal-halide complex, and removing the boundary layer.

5. The process of claim 4 , wherein the boundary layer comprises a dielectric and the refractory metal-halide complex comprises WF 6 .

6. The process of claim 2 , wherein the dielectric layer comprises a material selected from the group consisting of Ta 2 O 5 , BaTiO 3 , SrTiO 3 , Ba x Sr 1-x TiO 3 , and PbZr x Ti 1-x O 3 .

7. The process of claim 3 , wherein the metal layer comprises titanium.

8. The process of claim 1 , wherein making the silicon electrode structure rugged comprises seeding and annealing to form a hemispherically grained silicon layer.

9. The process of claim 1 , wherein the rugged silicon electrode structure comprises a hemispherical grain morphology.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2010
From: MICRON TECHNOLOGY, INC.
To: ROUND ROCK RESEARCH, LLC
Reel/Frame 023786/0416 →