IP Library › Assignment 023786/0416
Patent Assignment
Reel/Frame 023786/0416

Assignment of Assignor's Interest

Recorded: 2010-01-04 Pages: 274
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2009-12-23
Assignee
ROUND ROCK RESEARCH, LLC
26 DEER CREEK LANE, MT. KISCO, NEW YORK, 10549
Covered Properties (3452)
Display System and Memory Architecture and Method for Displaying Images in Windows on a Video Display
Patent: 4,823,108 →
Application: 07/169,304 →
Multibit Decorrelated Spur Digital Radio Frequency Memory
Patent: 4,885,587 →
Application: 07/288,376 →
Power Pack with Concealed Radio Transmitter for Portable Cellular Telephone
Patent: 5,001,772 →
Application: 07/437,599 →
Dram Cell Having a Texturized Polysilicon Lower Capacitor Plate for Increased Capacitance
Patent: 5,043,780 →
Application: 07/460,453 →
Parallel Digital Processor Including Lateral Transfer Buses with Interrupt Switches to Form Interconnection Segments
Patent: 5,247,689 →
Application: 07/478,232 →
High Efficiency Charge Pump Circuit
Patent: 5,023,465 →
Application: 07/498,772 →
High Efficiency Charge Pump Circuit
Patent: 5,038,325 →
Application: 07/498,773 →
Non-Contacting Radio Frequency Coupler Connector
Patent: 5,073,761 →
Application: 07/533,477 →
Process for Fabricating a Dram Array Having Feature Widths That Transcend the Resolution Limit of Available Photolithography
Patent: 5,013,680 →
Application: 07/555,980 →
High Performance Sub-Micron P-Channel Transistor with Germanium Implant
Patent: 5,266,510 →
Application: 07/566,433 →
Process for Fabricating, on the Edge of a Silicon Mesa, a Mosfet Which Has a Spacer-Shaped Gate and a Right-Angled Channel Path
Patent: 5,177,027 →
Application: 07/569,353 →
Method of Endpoint Detection During Chemical/Mechanical Planrization of Semiconductor Wafers
Patent: 5,036,015 →
Application: 07/586,996 →
Method of Manufacturing Edge Connected Semiconductor Die
Patent: 5,126,286 →
Application: 07/593,155 →
Semiconductor Package Utilizing Edge Connected Semiconductor Dice
Patent: 5,146,308 →
Application: 07/593,177 →
Method for Forming Self-Aligned Conducting Pillars in an (Ic) Fabrication Process
Patent: 5,100,838 →
Application: 07/594,424 →
High Efficiency Diode Phase Shifter
Patent: 5,066,930 →
Application: 07/600,650 →
Compensated Mixed Dielectric Overlay Coupler
Patent: 5,075,646 →
Application: 07/600,651 →
Low Power Memory Module Using Restricted Ram Activation
Patent: 5,257,233 →
Application: 07/608,125 →
Microcoprocessor, Memory Management Unit Interface to Support One or More Coprocessors
Patent: 5,283,881 →
Application: 07/643,624 →
Packaging Means for a Semiconductor Die Having Particular Shelf Structure
Patent: 5,107,328 →
Application: 07/655,494 →
Lateral Field Fbar
Patent: 5,233,259 →
Application: 07/656,657 →
Temperature-Dependent Dram Refresh Circuit
Patent: 5,278,796 →
Application: 07/684,422 →
Dynamic Ram Array for Emulating a Static Ram Array
Patent: 5,276,843 →
Application: 07/684,428 →
Secure Digital Conferencing System
Patent: 5,150,410 →
Application: 07/684,688 →
An Apparatus for Endpoint Detection During Mechanical Planarization of Semiconductor Wafers
Patent: 5,069,002 →
Application: 07/686,686 →
High Efficiency Charge Pump
Patent: 5,126,590 →
Application: 07/716,697 →
Dram Cell in Which a Silicon-Germanium Alloy Layer Having a Rough Surface Morphology Is Utilized for a Capacitive Surface
Patent: 5,130,885 →
Application: 07/727,701 →
Conductive Source Line for High Density Programmable Read-Only Memory Applications
Patent: 5,149,665 →
Application: 07/727,702 →
Method for Performing a Split Read/Write Operation in a Dynamic Random Access Memory
Patent: 5,276,642 →
Application: 07/730,366 →
Split Read/Write Dynamic Random Access Memory
Patent: 5,307,314 →
Application: 07/730,367 →
Dynamic Random Access Memory with Operational Sleep Mode
Patent: 5,262,998 →
Application: 07/744,989 →
Array of Read-Only Memory Cells, Each of Which Has a One-Time, Voltage Programmable Antifuse Element Constructed Within a Trench Shared by a Pair of Cells
Patent: 5,241,496 →
Application: 07/746,824 →
Electronic Identification Tag Interrogation Method
Patent: 5,266,925 →
Application: 07/769,986 →
Method of Making Self-Aligned Contacts and Vertical Interconnects to Integrated Circuits
Patent: 5,204,286 →
Application: 07/775,744 →
Semiconductor Floating Gate Device Having Improved Channel-Floating Gate Interaction
Patent: 5,260,593 →
Application: 07/805,298 →
Antifuse Programming by Transistor Snap-Back
Patent: 5,257,222 →
Application: 07/821,501 →
Two-Step Chemical Mechanical Polishing Process for Producing Flush and Protruding Tungsten Plugs
Patent: 5,244,534 →
Application: 07/824,980 →
Titanium/Aluminum/Nitrogen Material for Semiconductor Devices
Patent: 5,231,306 →
Application: 07/828,721 →
Method and System for Minimizing Power Demands on Portable Computers and the Like by Refreshing Selected Dram Cells
Patent: 5,148,546 →
Application: 07/836,536 →
Method of Forming a Buried Bit Line Array of Memory Cells
Patent: 5,250,457 →
Application: 07/838,549 →
Method for Programming Programmable Devices by Utilizing Single or Multiple Pulses Varying in Pulse Width and Amplitude
Patent: 5,257,225 →
Application: 07/850,739 →
Cell Structure for a Programmable Read Only Memory Device
Patent: 5,241,202 →
Application: 07/850,740 →
Optimized Container Stacked Capacitor Dram Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing
Patent: 5,162,248 →
Application: 07/850,746 →
Network Architecture Suitable for Multicasting and Resource Locking
Patent: 5,243,596 →
Application: 07/853,551 →
Integrated Circuit Polishing Method
Patent: 5,314,843 →
Application: 07/858,670 →
Integrated Circuit Fabrication Process to Reduce Critical Dimension Loss During Etching
Patent: 5,259,924 →
Application: 07/865,087 →
Multiple Register Block Write Method and Circuit for Video Drams
Patent: 5,282,177 →
Application: 07/865,092 →
Semiconductor Processing Method for Forming Substrate Isolation Trenches
Patent: 5,229,316 →
Application: 07/869,614 →
Heat Dissipating Lcd Display
Patent: 5,255,109 →
Application: 07/872,364 →
Method of Making Semiconductor Devices Having Two-Layer Gate Structure
Patent: 5,393,683 →
Application: 07/887,785 →
Soft Bond for Semiconductor Dies
Patent: 5,173,451 →
Application: 07/889,008 →
Method of Chemical Mechanical Polishing Aluminum Containing Metal Layers and Slurry for Chemical Mechanical Polishing
Patent: 5,209,816 →
Application: 07/893,449 →
Passive (Non-Contact) Recharging of Secondary Battery Cell(S) Powering Rfid Transponder Tags
Patent: 5,300,875 →
Application: 07/894,879 →
Method of Making Stacked Capacitors for Dram Cell
Patent: 5,198,386 →
Application: 07/895,520 →
Method for Reducing Conductive and Convective Heat Loss from the Battery in an Rfid Tag or Other Battery-Powered Devices
Patent: 5,323,150 →
Application: 07/897,224 →
Process for Selectively Etching a Layer of Silicon Dioxide on an Underlying Stop Layer of Silicon Nitride
Patent: 5,286,344 →
Application: 07/898,505 →
Single Mask Process for Forming Both N-Type and P-Type Gates in a Polycrystalline Silicon Layer During the Formation of a Semiconductor Device
Patent: 5,278,085 →
Application: 07/928,928 →
Transistor Antifuse for a Programmable Rom
Patent: 5,282,158 →
Application: 07/934,024 →
Four Poly Eprom Process and Structure Comprising a Conductive Source Line Structure and Self-Aligned Polycrystalline Silicon Digit Lines
Patent: 5,270,240 →
Application: 07/942,707 →
Thin Film Capacitors
Patent: 5,390,072 →
Application: 07/945,891 →
Reduced Mask Cmos Process for Fabricating Stacked Capacitor Multi- Megabit Dynamic Random Access Memories Utilizing Single Etch Stop Layer for Contacts
Patent: 5,292,677 →
Application: 07/947,523 →
Dual Mode Electronic Identification System
Patent: 5,317,309 →
Application: 07/948,345 →
Improved Method for Accessing Machine State Information
Patent: 5,404,526 →
Application: 07/963,646 →
Optimized Container Stacked Capacitor Dram Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing
Patent: 5,270,241 →
Application: 07/973,092 →
Soft Bond for Semiconductor Dies
Patent: 5,342,807 →
Application: 07/976,093 →
Removable Adhesives for Attachment of Semiconductor Dies
Patent: 5,336,649 →
Application: 07/976,221 →
Shallow Trench Source Eprom Cell
Patent: 5,297,082 →
Application: 07/976,226 →
Testing and Burn-in of Ic Chips Using Radio Frequency Transmission
Patent: 6,058,497 →
Application: 07/979,607 →
Method for Reducing, by a Factor or 2-N, the Minimum Masking Pitch of a Photolithographic Process
Patent: 5,328,810 →
Application: 07/981,976 →
Data Communication Method Using Identification Protocol
Patent: 5,500,650 →
Application: 07/990,915 →
Data Communication System Using Identification Protocol
Patent: 5,365,551 →
Application: 07/990,918 →
Packet-Switched Ring Network Having Direct Access to Low and High Bandwidth Memories
Patent: 5,406,322 →
Application: 07/995,673 →
Method for Selectively Etching Polysilicon to Gate Oxide Using an Insitu Ozone Photoresist Strip
Patent: 5,346,586 →
Application: 07/996,074 →
Method for Identifying a Semiconductor Die Using an Ic with Programmable Links
Patent: 5,301,143 →
Application: 07/999,214 →
Low Power Memory Array Using Selective Device Activation
Patent: 5,414,670 →
Application: 08/000,066 →
Battery Package and Method Using Flexible Polymer Films Having a Deposited Layer of an Inorganic Material
Patent: 5,326,652 →
Application: 08/008,529 →
System for Repeatable Temperature Measurement Using Surface Reflectivity
Patent: 5,364,187 →
Application: 08/028,040 →
Method for Repeatable Temperature Measurement Using Surface Reflectivity
Patent: 5,350,236 →
Application: 08/028,051 →
One Time Programmable Fully-Testable Programmable Logic Device with Zero Power and Anti-Fuse Cell Architecture
Patent: 5,315,177 →
Application: 08/030,896 →
Modulated Spread Spectrum in Rf Identification Systems Method
Patent: 5,539,775 →
Application: 08/032,384 →
Method for Attaching a Semiconductor Die to a Leadframe Using a Patterned Adhesive Layer
Patent: 5,286,679 →
Application: 08/033,140 →
Semiconductor Electrical Interconnection Methods
Patent: 5,244,837 →
Application: 08/033,830 →
Method for Shaping Features of a Semiconductor Structure Using Chemical Mechanical Planarization (Cmp)
Patent: 5,302,233 →
Application: 08/034,421 →
Multi-Chip Stacked Devices
Patent: 5,291,061 →
Application: 08/043,503 →
Memory Device with Pulse Circuit for Timing Data Output, and Method for Outputting Data
Patent: 5,349,566 →
Application: 08/064,484 →
Local Bus Interface
Patent: 5,649,162 →
Application: 08/066,400 →
Reducing Current Supplied to an Integrated Circuit
Patent: 5,446,367 →
Application: 08/067,194 →
Method for Fabricating a Leadless Battery Employing an Alkali Metal Anode and Polymer Film Inks
Patent: 5,624,468 →
Application: 08/071,463 →
Multichip Module Having a Stacked Arrangement
Patent: 5,323,060 →
Application: 08/071,580 →
Method of Isolating Semiconductor Devices and Arrays of Memory Integrated Circuitry
Patent: 5,292,683 →
Application: 08/071,752 →
Low Resistance Device Element and Interconnection Structure
Patent: 5,341,016 →
Application: 08/078,700 →
Polymer-Lithium Batteries and Improved Methods for Manufacturing Batteries
Patent: 5,350,645 →
Application: 08/081,007 →
Verifying Dynamic Memory Refresh
Patent: 5,335,202 →
Application: 08/084,399 →
Controlling Dynamic Memory Refresh Cycle Time
Patent: 5,392,251 →
Application: 08/091,697 →
Low Resistance Electrodes Useful in Flat Panel Displays
Patent: 5,342,477 →
Application: 08/092,311 →
Planarization of a Gate Electrode for Improved Gate Patterning Over Non-Planar Active Area Isolation
Patent: 5,346,587 →
Application: 08/105,276 →
Method for Improving Latchup Immmunity in a Dual-Polysilicon Gate Process
Patent: 5,420,061 →
Application: 08/106,179 →
Method for Forming Enhanced Capacitance Stacked Capacitor Structures Using Hemi-Spherical Grain Polysilicon
Patent: 5,340,765 →
Application: 08/106,503 →
System and Method for Real-Time Control of Semiconductor a Wafer Polishing, and a Polishing Head
Patent: 5,486,129 →
Application: 08/112,759 →
Method of Making a Cell Structure for a Programmable Read Only Memory Device
Patent: 5,360,751 →
Application: 08/114,263 →
One-Time, Voltage-Programmable, Logic Element
Patent: 5,331,196 →
Application: 08/114,886 →
Enclosed Transciever
Patent: 5,448,110 →
Application: 08/123,030 →
Method of Processing a Semiconductor Wafer to Form an Array of Nonvolatile Memory Devices Employing Floating Gate Transistors and Peripheral Area Having Cmos Transistors
Patent: 5,292,681 →
Application: 08/123,611 →
Chemical-Mechanical Polishing Processes of Planarizing Insulating Layers
Patent: 5,395,801 →
Application: 08/130,117 →
Apparatus and Method for Error Detection and Correction in Radio Frequency Identification Device
Patent: 5,479,416 →
Application: 08/130,124 →
Method to Form a Low Resistant Bond Pad Interconnect
Patent: 5,384,284 →
Application: 08/130,225 →
Germanium Implanted Stacked Capacitor Cell
Patent: 5,364,814 →
Application: 08/132,682 →
Low Voltage Charge Pump Circuit and Method for Pumping a Node to an Electrical Potential
Patent: 5,394,320 →
Application: 08/137,565 →
Anti-Theft Method for Detecting the Unauthorized Opening of Containers and Baggage
Patent: 5,406,263 →
Application: 08/151,599 →
N-Channel Field Effect Transistor Having an Oblique Arsenic Implant for Lowered Series Resistance
Patent: 5,376,566 →
Application: 08/152,116 →
Method for Enhancing Oxide to Nitride Selectivity Through the Use of Independent Heat Control
Patent: 5,880,036 →
Application: 08/152,755 →
Silver-Iron Battery
Patent: 5,429,894 →
Application: 08/161,016 →
Separator Systems for Silver-Iron Batteries
Patent: 5,426,004 →
Application: 08/161,019 →
System Powered with Inter-Coupled Charge Pumps
Patent: 5,493,249 →
Application: 08/164,163 →
Arrays of Memory Integrated Circuitry
Patent: 5,397,908 →
Application: 08/164,896 →
Hardware Implemented Row Copy Enable Mode for Drams to Create Repetitive Backgrounds for Video Images or Dram Testing
Patent: 5,381,368 →
Application: 08/165,773 →
Method to Prepare Hemi-Spherical Grain (Hsg) Silicon Using a Fluorine Based Gas Mixture and High Vacuum Anneal
Patent: 5,407,534 →
Application: 08/166,058 →
Programmable Logic Device Macrocell with an Exclusive Feedback Line and an Exclusive External Input Line
Patent: 5,331,227 →
Application: 08/166,662 →
Process of Manufacturing an Electrical Bonding Interconnect Having a Metal Bond Pad Portion and Having a Conductive Epoxy Portion Comprising an Oxide Reducing Agent
Patent: 5,480,834 →
Application: 08/166,747 →
Active Pull-Up Voltage Spike Reducer
Patent: 5,444,408 →
Application: 08/167,262 →
Electrically Powered Postage Stamp or Mailing or Shipping Label Operative with Radio Frequency (Rf) Communication
Patent: 5,497,140 →
Application: 08/168,909 →
Optical End Point Detection Methods in Semiconductor Planarizing Polishing Processes
Patent: 5,413,941 →
Application: 08/178,663 →
Barrier Process for TA2O5 Capacitor
Patent: 5,362,632 →
Application: 08/193,678 →
Methods of Producing Button-Type Batteries and a Plurality of Battery Terminal Housing Members
Patent: 5,603,157 →
Application: 08/205,590 →
Button-Type Battery with Improved Separator and Gasket Construction
Patent: 5,547,781 →
Application: 08/205,611 →
Button-Type Battery Having Bendable Construction, and Angled Button-Type Battery
Patent: 5,432,027 →
Application: 08/205,957 →
Method of Producing Button-Type Batteries and Spring-Biased Concave Button-Type Battery
Patent: 5,486,431 →
Application: 08/206,051 →
Method of Making Shallow Trench Source Eprom Cell
Patent: 5,445,981 →
Application: 08/208,753 →
Circuitry for Initializing Burst Mode Operations to Active Portions of a Memory Array
Patent: 5,896,551 →
Application: 08/228,051 →
Semiconductor Processing Methods of Forming Stacked Capacitors
Patent: 5,498,562 →
Application: 08/237,371 →
Data Output Buffer
Patent: 5,513,140 →
Application: 08/252,421 →
Process for Fabricating Storage Capacitor Structures Using Cvd Tin on Hemispherical Grain Silicon
Patent: 5,418,180 →
Application: 08/259,766 →
Data Communication System Using Identification Protocol
Patent: 5,583,850 →
Application: 08/263,210 →
Apparatus and Method for Providing Multi-Level Security for Communication Among Computers and Terminals on a Network
Patent: 5,577,209 →
Application: 08/270,398 →
Method of Forming Button-Type Battery Lithium Electrodes
Patent: 5,480,462 →
Application: 08/271,012 →
Circuit Having a Control Array of Memory Cells and a Current Source and a Method for Generating a Self-Refresh Timing Signal
Patent: 5,455,801 →
Application: 08/275,576 →
Lockout Circuit and Method for Preventing Metastablilty During the Termination of a Refresh Mode
Patent: 5,400,289 →
Application: 08/275,693 →
Method and Apparatus for Attaching a Radio Frequency Transponder to an Object
Patent: 6,239,737 →
Application: 08/275,986 →
Communication System Having Transmitter Frequency Control
Patent: 5,568,512 →
Application: 08/281,384 →
Lead Finger Tread for a Semiconductor Lead Package System
Patent: 5,559,366 →
Application: 08/285,974 →
Drams Having on-Chip Row Copy Circuits for Use in Testing and Video Imaging and Method for Operating Same
Patent: 5,440,517 →
Application: 08/290,388 →
Formation Methods of Opaque or Translucent Films
Patent: 5,591,680 →
Application: 08/294,126 →
Polishing Apparatus, a Polishing Wafer Carrier Apparatus, a Replaceable Component for a Particular Polishing Apparatus and a Process of Polishing Wafers
Patent: 5,533,924 →
Application: 08/299,506 →
In-Sheet Transceiver Testing
Patent: 5,983,363 →
Application: 08/306,906 →
Double Mask Process for Forming Trenches and Contacts During the Formation of a Semiconductor Memory Device
Patent: 5,466,639 →
Application: 08/319,217 →
Method of Forming Button-Type Batteries
Patent: 5,494,495 →
Application: 08/321,251 →
Process for Dram Incorporating a High-Energy, Oblique P-Type Implant for Both Field Isolation and Punchthrough
Patent: 5,439,835 →
Application: 08/324,277 →
System with Chip to Chip Communication
Patent: 5,621,913 →
Application: 08/340,016 →
Method to Prepare Hemi-Spherical Grain (Hsg) Silicon Using a Fluorine Based Gas Mixture and High Vacuum Anneal
Patent: 5,629,223 →
Application: 08/340,103 →
Modulated Spread Spectrum in Rf Identification Systems Method
Patent: 5,825,806 →
Application: 08/348,274 →
Synchronous Nand Dram Architecture
Patent: 5,513,148 →
Application: 08/348,552 →
Method of Narrowing Flash Memory Device Threshold Voltage Distribution
Patent: 5,633,823 →
Application: 08/348,649 →
Spacers for Large Area Displays
Patent: 5,486,126 →
Application: 08/349,091 →
A System for Bypassing Setup States in a Bus Operation
Patent: 5,581,793 →
Application: 08/353,160 →
Method for Narrowing Threshold Voltage Distribution in a Block Erased Flash Memory Array
Patent: 5,680,350 →
Application: 08/355,752 →
Multi-Drive Virtual Mass Storage Device and Method of Operating Same
Patent: 5,671,439 →
Application: 08/370,650 →
Burst Edo Memory Device
Patent: 5,526,320 →
Application: 08/370,761 →
Serial to Parallel Conversion with Phase Locked Loop
Patent: 5,598,156 →
Application: 08/372,412 →
Timing Control for a Matrixed Scanned Array
Patent: 5,638,085 →
Application: 08/372,413 →
Burst Edo Memory Device Having Pipelined Output Buffer
Patent: 5,652,724 →
Application: 08/386,563 →
Burst Edo Memory Device with Maximized Write Cycle Timing
Patent: 5,610,864 →
Application: 08/386,894 →
On-Chip Memory Redundancy Circuitry for Programmable Non-Volatile Memories, and Methods for Programming Same
Patent: 5,513,144 →
Application: 08/387,244 →
Low Voltage Charge Pump Circuit and Method for Pumping a Node to an Electrical Potential
Patent: 5,537,306 →
Application: 08/393,573 →
Method of Forming a Button-Type Battery and a Button-Type Battery with Improved Separator Construction
Patent: 5,755,831 →
Application: 08/394,543 →
Dynamic Memory Device Including Apparatus for Controlling Refresh Cycle Time
Patent: 5,539,703 →
Application: 08/395,369 →
Dielectric Material and Process to Create Same
Patent: 5,686,748 →
Application: 08/395,933 →
Shallow Trench Source Eprom Cell
Patent: 5,596,213 →
Application: 08/403,328 →
Optimization Circuitry and Control for a Synchronous Memory Device with Programmable Latency Period
Patent: 5,544,124 →
Application: 08/403,382 →
Structurally Stable Gelled Electrolytes
Patent: 5,648,011 →
Application: 08/407,484 →
Memory Array Using Selective Device Activation
Patent: 5,566,122 →
Application: 08/407,721 →
Method and Apparatus for Mounting a Component to a Substrate Using an Anisotropic Adhesive, a Compressive Cover Film, and a Conveyor
Patent: 5,605,547 →
Application: 08/410,889 →
Active Pull-Up Voltage Spike Reducer
Patent: 5,525,926 →
Application: 08/417,571 →
System Powered with Inter-Coupled Charge Pumps
Patent: 5,642,073 →
Application: 08/418,143 →
Anti-Theft Method for Detecting the Unauthorized Opening of Containers and Baggage
Patent: 5,646,592 →
Application: 08/421,571 →
Spherical Antenna Pattern(S) from Antenna(S) Arranged in a Two-Dimensional Plane for Use in Rfid Tags and Labels
Patent: 5,572,226 →
Application: 08/422,007 →
Wake Up Device for a Communications System
Patent: 5,790,946 →
Application: 08/424,827 →
Improved Electronic Data Interchange System for Managing Non-Standard Data
Patent: 5,557,780 →
Application: 08/426,469 →
Gain Adjustment Method in Two-Way Communication Systems
Patent: 5,613,228 →
Application: 08/430,711 →
Low Power, High Speed Level Shifter
Patent: 5,528,173 →
Application: 08/438,645 →
Multi-Bit Block Write in a Random Access Memory
Patent: 5,559,749 →
Application: 08/439,358 →
Storage Capacitor Structures Using Cvd Tin on Hemispherical Grain Silicon
Patent: 5,608,247 →
Application: 08/440,573 →
Enhanced Multiple Block Writes to Adjacent Blocks of Memory Using a Sequential Counter
Patent: 5,657,287 →
Application: 08/455,095 →
System Adapted to Receive Multiple Memory Types, and Method for Determining a Type of Memory Present
Patent: 6,804,760 →
Application: 08/457,650 →
Publication: US 2003/0084233
Burst Edo Memory Device Address Counter
Patent: 5,675,549 →
Application: 08/457,651 →
Method for Fabricating an Array of Ultra-Small Pores for Chalcogenide Memory Cells
Patent: 5,879,955 →
Application: 08/473,077 →
Polysilicon Pillar Diode for Use in a Non-Volatile Memory Cell
Patent: 5,751,012 →
Application: 08/474,028 →
Method and Apparatus for a High Speed Cyclical Redundancy Check System
Patent: 5,854,800 →
Application: 08/474,397 →
Auto-Precharge During Bank Selection
Patent: 5,636,173 →
Application: 08/480,154 →
Auto-Activate on Synchronous Dynamic Random Access Memory
Patent: 5,600,605 →
Application: 08/481,920 →
Display System and Memory Architecture and Method for Displaying Images in Windows on a Video Display
Patent: 5,847,705 →
Application: 08/484,948 →
Chalcogenide Memory Cell with a Plurality of Chalcogenide Electrodes
Patent: 5,789,758 →
Application: 08/486,375 →
Method and Apparatus for Forming an Integrated Circuit Electrode Having a Reduced Contact Area
Patent: 6,420,725 →
Application: 08/486,635 →
Memory Array Having a Multi-State Element and Method for Forming Such Array or Cells Thereof
Patent: 5,869,843 →
Application: 08/486,639 →
Local Word Line Phase Driver
Patent: 5,586,080 →
Application: 08/494,535 →
Method of Lithography Using Reticle Pattern Blinders
Patent: 5,667,918 →
Application: 08/495,040 →
Reducing Current Supplied to an Integrated Circuit
Patent: 5,563,499 →
Application: 08/496,741 →
Distributed Write Data Drivers for Burst Access Memories
Patent: 5,598,376 →
Application: 08/497,354 →
Method and Apparatus for Multiple Latency Synchronous Pipelined Dynamic Random Access Memory
Patent: 5,655,105 →
Application: 08/497,534 →
Page Mode Editable Real Time Read Transfer
Patent: 5,612,922 →
Application: 08/498,178 →
Method and Apparatus for Writing and Erasing Flash Memory
Patent: 5,650,967 →
Application: 08/498,596 →
Data Input/Output Circuit for Performing High Speed Memory Data Read Operation
Patent: 5,663,908 →
Application: 08/499,025 →
Method for Mounting and Electrically Interconnecting Semiconductor Dice
Patent: 5,661,901 →
Application: 08/499,931 →
Methods of Forming Complementary Metal Oxide Semiconductor (Cmos) Integrated Circuitry
Patent: 5,534,449 →
Application: 08/503,419 →
Address Transition Detection in a Synchronous Design
Patent: 5,729,503 →
Application: 08/506,438 →
Memory System Having Programmable Control Parameters
Patent: 5,801,985 →
Application: 08/508,828 →
Memory Circuit with Switch for Selectively Connecting an Input/Output Pad Directly to a Nonvolatile Memory Cell
Patent: 5,594,694 →
Application: 08/508,848 →
Memory System Having Internal State Monitoring Circuit
Patent: 5,619,461 →
Application: 08/508,924 →
Reference Voltage Generator Using Flash Memory Cells
Patent: 5,721,702 →
Application: 08/509,737 →
Data Communication for Memory
Patent: 5,724,288 →
Application: 08/512,326 →
Method for Packaging a Semiconductor Die
Patent: 5,696,033 →
Application: 08/515,812 →
On-Chip Program Voltage Generator for Antifuse Repair
Patent: 5,604,693 →
Application: 08/516,005 →
Single Deposition Layer Metal Dynamic Random Access Memory
Patent: 6,388,314 →
Application: 08/516,171 →
Method for Mounting a Battery on a Substrate
Patent: 5,558,679 →
Application: 08/517,504 →
Integrated Circuit Memory with Back End Mode Disable
Patent: 5,657,293 →
Application: 08/518,157 →
Memory Having and Method for Providing a Reduced Access Time
Patent: 5,745,429 →
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Modulated Spread Spectrum in Rf Identification Systems Method
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High Density Semiconductor Memory and Method of Making
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Capacitors, Dram Arrays, Monolithic Integrated Circuits, and Methods of Forming Capacitors, Dram Arrays, and Monolithic Integrated Circuits
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Method for Implementing a Graphic Address Remapping Table as a Virtual Register File in System Memory
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Method of Forming Thin Profile Batteries and Methods of Providing Sealing Gaskets Between Terminal Housing Members
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Address Strobe Recognition in a Memory Device
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Architecture and Package Orientation for High Speed Memory Devices
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Dpsk Demodulator Which May Be Used in an Interrogator of a Remote Intelligence Communication System
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Memory Device with Dual Timing and Signal Latching Control
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Method of Managing Power for a Computer System and Generating Application Threshold Warnings
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User-Selectable Power Management Interface with Application Threshold Warnings
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Concurrent Dithering and Scale Correction of Pixel Color Values
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Transistor with Silicon Oxycarbide Gate and Methods of Fabrication and Use
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Gate Stock with Improved Sidewall Integrity
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Method for Configuration of Peripherals by Interpreting Response from Peripherals to Enable Selection of Driver File and Altering Configuration File to Enable Loading of Selected Driver File
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Method for a Primary Bios Rom Recovery in a Dual Bios Rom Computer System
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Method for Multithreaded Disk Drive Operation in a Computer System
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Wireless Communication System, Radio Frequency Communications System, Wireless Communications Method, Radio Frequency Communications Method,
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Method for Removing Marks from Integrated Circuit Devices and Devices So Processed
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Radio Frequency Identification Transceiver and Antenna
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Method and System for Filtering Unauthorized Electronic Mail Messages
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Method of Controlling Access to a Movable Container and to a Compartment of a Vehicle, and a Secure Cargo Transportation System
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Radio Frequency-Transmissive Compositions, Methods of Forming Radio Frequency-Transmissive Compositions, Microelectronic Devices, Wireless Radio Frequency Communication Devices, and Methods of Forming Microelectronic Devices, Wireless Radio Frequency Communicatio
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Fuse Option for Multiple Logic Families on the Same Die
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Encapsulated Electronic Component and Method for Encapsulating an Electronic Component
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Wireless Communication Devices and Methods of Forming Wireless Communication Devices
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Self-Enabling Pulse- Trapping Circuit
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Method of Forming Titanium Silicide and Titanium by Chemical Vapor Deposition
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Adjustable Delay Circuit for Setting the Speed Grade of a Semiconductor Device
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Multi-Drive Virtual Mass Storage Device and Method of Operating Same
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Vertically Mountable Semiconductor Device, Assembly, and Methods
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Method of Modifying an Rf Circuit of a Plasma Chamber to Increase Chamber Life and Process Capabilities
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Fiber Spacers in Large Area Vacuum Displays and Method for Manufacture of Same
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Vehicles, License Plate Frame Assemblies, Methods of Forming License Plate Frames, and Methods of Attaching Rfids, Transponders and Modulators to Vehicles
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Method and System for Displaying Information Uniformly on Tethered and Remote Input Devices
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Chamber and Cleaning Process Therefor
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Chemical Vapor Deposition of Titanium
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Method and Apparatus for Trench Isolation Process with Pad Gate and Trench Edge Spacer Elimination
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Method and Apparatus for Adjusting Data Timing by Delaying Clock Signal
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Flash Memory System and Method for Monitoring the Disturb Effect on Memory Cell Blocks Due to High Voltage Conditions of Other Memory Cell Blocks
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Inductor Formed at Least Partially in a Substrate
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Method and Apparatus to Display Processing Parameter
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Wireless Communication and Identification Packages, Communication Systems, Methods of Communicating, and Methods of Forming a Communication Device
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Bit Synchronizers and Methods of Synchronizing and Calculating Error
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Process for Aligning and Sealing Components in a Display Device
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Insulative Sealing Gaskets and a Thin Profile Battery
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Recovery of Useful Areas of Partially Defective Synchronous Memory Components
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Method for Recovery of Useful Areas of Partially Defective Synchronous Memory Components
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Semiconductor Chip
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Circuit and Method for Specifying Performance Parameters in Integrated Circuits
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Low Cost Dram Metallization
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Method of Making Chalcogenide Memory Device
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Flash Memory with Adjustable Write Operation Timing
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Method for Initializing and Reprogramming a Control Operation Feature of a Memory Device
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Integrated Circuit Data Latch Driver Circuit
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Methods of Forming Batteries
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Battery Comprising Ink
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Apparatus for Assisting Video Compression in a Computer System
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Method for Assisting Video Compression in a Computer System
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Integrated Circuitry Comprising Halo Regions and Ldd Regions
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Method and System for Identifying Lost or Stolen Devices
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Integrated Circuit Package and Method of Fabrication
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Circuits and Methods for Dual-Gated Transistors
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Method for Swapping, Adding or Removing a Processor in an Operating Computer System
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Vertical Surface Mount Assembly and Methods
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Centralized, Automated Installation of Software Products
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Stackable Chip Scale Semiconductor Package with Mating Contacts on Opposed Surfaces
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Method of Peer-to-Peer Mastering Over a Computer Bus
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System for Peer-to-Peer Mastering Over a Computer Bus
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Method and Apparatus for Coupling a Semiconductor Die to Die Terminals
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High Selectivity Bpsg to Teos Etchant
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Dual Floating Gate Programmable Read Only Memory Cell Structure and Method for Its Fabrication and Operation
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Semiconductor Processing Methods of Forming a Conductive Gate and Line
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On-Chip Substrate Regular Test Mode
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Synchronous Dynamic Random Access Memory Device
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Method of Communications in a Backscatter System, Interrogator, and Backscatter Communications System
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Method and System for Concurrent Computer Transaction Processing
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Backscatter Interrogators, Communication Systems and Backscatter Communication Methods
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Interrogators Communication Systems Communication Methods and Methods of Processing a Communication Signal
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Advanced Programmable Interrupt Controller
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Method for Notifying an Individual of a Previously Scheduled Event
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System for Decoding Addresses for a Defective Memory Array
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System for Notifing an Individual of a Previously Scheduled Event
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Method for Decoding Addresses for a Defective Memory Array
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Isolation Regions and Methods of Forming Isolation Regions
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Stacked Leads-Over Chip Milti-Chip Module
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Method and Apparatus for Remote Data Telemetry and Point of Sale Method and Apparatus
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Stackable Ball Grid Array Package
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Scalable High Dielectric Constant Capacitor
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Method of Forming Capacitors, Method of Processing Dielectric Layers, Method of Forming a Dram Cell
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Mask Having a Tapered Profile Used During the Formation of a Semiconductor Device
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Methods of Electrically Contacting to Conductive Plugs, Methods of Forming Contact Openings, and Methods of Forming Dynamic Random Access Memory Circuitry
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Memory and Other Integrated Circuitry Having a Conductive Interconnect Line Pitch of Less Than 0.6 Micron
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Dram Capacitors Made from Silicon-Germanium and Electrode-Limited Conduction Dielectric Films
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Multi-Bank Architecture for a Wide I/O Dram
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Wireless Communication Systems, Interfacing Devices, Communication Methods, Methods of Interfacing with an Interrogator, and Methods of Operating an Interrogator
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Publication: US 2002/0057191
Electronic Mail Attachment Verifier
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Apparatus for Updating Wallpaper for Computer Display
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Method for Updating Wallpaper for Computer Display
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Method of Communications in a Backscatter System, Interrogator, and Backscatter Communications System
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Apparatus and Method for Generating a Clock Within a Semiconductor Device and Devices and Systems Including Same
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Indirect Activation of a Getter Wire in a Hermetically Sealed Field Emission Display
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Wafer Level Fabrication and Assembly of Chip Scale Packages
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Photolithographic Method
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System for a Primary Bios Rom Recovery in a Dual Bios Rom Computer System
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Stand Alone Security Device for Computer Networks
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Clock Vernier Adjustment
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Web-Format Polishing Pads and Methods for Manufacturing and Using Web-Format Polishing Pads in Mechanical and Chemical-Mechanical Planarization of Microelectronic Substrates
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Dram Capacitor Formulation Using a Double-Sided Electrode
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Method of Forming Dynamic Random Access Memory Circuitry and Dynamic Random Access Memory
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Method and Apparatus for Accessing One of a Plurality of Memory Units Within an Electronic Memory Device
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Method for Time Multiplexing a Low-Speed and a High-Speed Bus Over Shared Signal Lines of a Physical Bus
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Time-Multiplexed Multi-Speed Bus
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Method for Removing Power and Signals from an Inadvertently Swapped Bus Card
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Computer System Having a Plurality of Bus Agents Coupled to Bus Requesters Wherein Each Bus Agent Includes an Internal Arbiter That Selects One of the Bus Requests
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Apparatus for Sensing Movement of a Bus Card and Automatically Removing Power from the Bus Card
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Bitline Contact Structures and Dram Array Structures
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Integrated Circuit Implementing Internally Generated Commands
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Button-Type Battery with Improved Separator and Gasket Construction
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Memory-Cell Array and a Method for Repairing the Same
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Methods of Forming Flip Chip Bumps and Related Flip Chip Bump Constructions
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M Ethod to Achieve Rough Silicon Surface on Both Sides of Container for Enhanceed Capacitance/Area Electrodes
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Method to Protect Gate Stack Material During Source/Drain Reoxidation
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Memory System Having Internal State Monitoring Circuit
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Method of Forming Button-Type Batteries and a Button-Type Battery Insulating and Sealing Gasket
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Method of Forming Cmos Integrated Circuitry
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Method for Information Reception in a Portable Computer
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Portable Computer Supporting Paging Functions
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Publication: US 2001/0045884
Self-Aligned Process for Making Contacts to Silicon Substrates During the Manufacture of Integrated Circuits Therein
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Method and Apparatus for Controlling the Data Rate of a Clocking Circuit
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Memory System Having Programmable Control Parameters
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Computer System Diagnostics
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Per Pixel Mip Mapping and Trilinear Filtering Using Scanline Gradients for Selecting Appropriate Texture Maps
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Communications System and Method, Fleet Management System and Method, and Method of Impeding Theft of Fuel
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Method for Adaptive Decoding of Memory Addresses
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Apparatus for Adaptive Decoding of Memory Addresses
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Processing Methods of Forming Contact Openings and Integrated Circuitry
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System and Method for Remapping Defective Memory Locations
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Three-Dimensional Container Diode for Use with Multi-State Material a Non-Volatile Memory Cell
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Gain Adjustment Method in Two-Way Communication Systems
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Method for Decoding Addresses
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Apparatus for Decoding Addresses
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Semiconductor Processing Methods of Forming Integrated Circuitry A
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Electrical Bonding Interconnect Having a Metal Bond Pad Portion and Having a Conductive Epoxy Portion Comprising an Oxide Reducing Agent
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Isolation Regions and Methods of Forming Isolation Regions
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Method of Manufacturing an Enclosed Transceiver
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Method for Patterning Cavities and Enhanced Cavity Shapes for Semiconductor Devices
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Apparatus for the Hot Swap and Add of Input/Output Platforms and Devices
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Methods of Forming Floating Gate Transistors
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Method for the Hot Swap and Add of Input/Output Platforms and Devices
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Method of Forming Dynamic Random Access Memory Circuitry and Dynamic Random Access Memory
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Method for Determining Status of Multiple Interlocking Fifo Buffer Structures Based on the Position of at Least One Pointer of Each of the Multiple Fifo Buffers
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Wireless Communication Devices, Radio Frequency Identification Devices, and Methods of Forming Wireless Communication Devices and Radio Frequency Identification Devices
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Circuitry Interconnection Method
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Method for Memory Error Handling
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Electronic Apparatus, Battery Powerable Apparatus, and Radio Frequency Communication Device
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Apparatus and Method for Reducing Removal Forces for Cmp Pads
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Method and Apparatus for Improving Latchup Immunity in a Dual-Polysilicon Gate Process
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Apparatus Improving Latchup Immunity in a Dual-Polysilicon Gate
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Publication: US 2002/0003266
Method for Sharing Data Buffers from a Buffer Pool
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System for Sharing Data Buffers from a Buffer Pool
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Capacitor Structures, Dram Cell Structures and Integrated Circuitry
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Field Emission Display with Non-Evaporable Getter Material
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Field Emission Display with Non-Evaporable Getter Material
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Pipelined Memory Controller
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Method and System for Establishing a Security Perimeter in Computer Networks
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Method of Processing Memory Requests in a Pipelined Memory Controller
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Mixed Enclave Operation in a Computer Network
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Memory Paging Control Method
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Memory Paging Control Apparatus
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Voltage Pump and a Level Translator Ircuit
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Publication: US 2002/0014907
Buffer with Adjustable Slew Rate and a Method of Providing an Adjustable Slew Rate
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Processor with Internal Register for Peripheral Status
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Method for Operating Processor with Internal Register for Peripheral Status
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Dual Floating Gate Programmable Read Only Memory Cell Structure and Method for Its Fabrication and Operation
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Method for Surface Mounting Electrical Components to a Substrate
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Polishing Pad and a Method for Making a Polishing Pad with Covalently Bonded Particles
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Embedded Dram Architecture with Local Data Drivers and Programmable Number of Data Read and Data Write Lines
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On-Time Delivery, Tracking and Reporting
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Method of Fabricating Transistor with Silicon Oxycarbide Gate
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Porous Silicon Dioxide Insulator
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Method of Low Angle, Low Energy Physical Vapor of Alloys Including Redepositing Layers of Different Compositions in Trenches
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Method of Emulating a Dual-Port Memory Device Using an Internally Cached Static Random Access Memory Architecture
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Block Write Circuit and Method for Wide Data Path Memory Devices
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Low Skew Differential Receiver with Disable Feature
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Method and Apparatus for Resynchronizing a Plurality of Clock Signals Used to Latch Respective Digital Signals, and Memory Device Using Same
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Memory Device with Block Write Burst
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High Performance Packaging for Microprocessors and Dram Chips Which Minimizes Timing Skews
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Structure and Method for Improved Signal Processing
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Electrical Interconnections
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Polishing Chucks, Semiconductor Wafer Polishing Chucks, Abrading Methods, Polishing Methods,Semiconductor Wafer Polishing Methods,and Methods of Forming Polishing Chucks
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Method and Apparatus for Planarizing and Cleaning Microelectronic Substrates
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Method to Reduce Floating Grain Defects in Dual-Sided Container Capacitor Fabrication
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Publication: US 2002/0031895
Battery Electrodes, Batteries, and Methods of Forming Batteries and Battery Electrodes
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Multi-Bit Block Write in a Random Access Memory
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Method for Producing an Integrated Circuit Assembly
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Low Power, High Speed Level Shifter
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Memory Device with Command Buffer
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Adjustable Output Driver Circuit Having Parallel Pull-Up and Pull-Down Elements
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Method and Apparatus for Resynchronizing a Plurality of Clock Signals Used in Latching Respective Digital Signals Applied to a Packetized Memory Device
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Backscatter Communication Systems, Interrogators, Methods of Communicating in a Backscatter System, and Backscatter Communication Methods
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Method and Apparatus for Generating Expect Data from a Captured Bit Pattern, and Memory Device Using Same
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Memory Device Having a Relatively Wide Data Bus
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Methods, Apparatuses and Substrate Assembly Structures for Fabricating Microelectronic Components Using Mechanical and Chemical-Mechanical Planarization Processes
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Method for Fabricating Floating Gate Semiconductor Devices with Trench Isolation Structures and Self Aligned Floating Gates
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Local Bus Interface
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Method and Apparatus for Multiple Latency Synchronous Dynamic Random Access Memory
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Method and Apparatus for Adaptively Adjusting the Timing Offset Between a Clock Signal and Digital Signals Transmitted Coincident with That Clock Signal, and Memory Device and System Using Same
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Radio Frequency Data Communications Device
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Radio Frequency Data Communications Device
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Method of Making a Schottky Diode in an Integrated Circuit
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Radio Frequency Data Communications Device
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Preventing Movement of Integrated Circuit Packages Relative to Their Support Surface
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Integrated Circuit Package Support System
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Integrated Circuit Package Support System
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Method of Speeding Power-Up of an Amplifier ,and Amplifier
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Radio Frequency Data Communications Device
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Method for Realizing an Improved Radio Frequency Detector for Use in a Radio Frequency Indentification Device, Frequency Lock Loop, Ingrated Circuit, Timing Oscillator, Method of Constructing a Frequency Lock Loop and Method of Operating an Integrated Circuit
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Stage Having Controlled Variable Resistance Load Circuit for Use in Voltage Controlled Ring Oscillator
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Method of Processing System Management Interrupt Requests
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Computer System for Processing System Management Interrupt Requests
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Stacked Leads-Over Chip Multi-Chip Module
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Pseudo Random Number Generator
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Frequency Doubler and Method of Doubling Frequency
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Data Communication for Memory
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Radio Frequency Data Communications Device
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Rugged Metal Electrodes for Metal-Insulator-Metal Capacitors
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Radio Frequency Data Communications Device
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Radio Frequency Data Communications Device
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Methods of Reducing Proximity Effects in Lithographic Processes
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Methods and Apparatuses for Mechanical and Chemical-Mechanical Planarization of Microelectronic-Device Substrate Assemblies on Planarizing Pads
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Communication System Including Diversity Antenna Queuing
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Method and Apparatus for a Chip-on-Board Semiconductor Module
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Method and System for Storing and Processing Multiple Memory Addresses
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Partially Ordered Cams Used in Ternary Hierarchical Address Searching/Sorting
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Methods of Enhancing Data Retention of a Floating Gate Transistor, Methods of Forming Floating Gate Transistors, and Floating Gate Transistors
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Radio Frequency Antenna with Current Controlled Sensitivity
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A Method for Prioritizing Data Transfer Request by Comparing a Latency Indentifier Value Received from an I/O Device with a Perdetermined Range of Values
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Apparatus for Controlling Data Transfer Operations Between a Memory and Devices Having Respective Latencies
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Integrated Device and Method for Routing a Signal Through the Device
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Publication: US 2001/0008482
Method of Forming a Contact Using a Sacrificial Spacer
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Methods of Forming Carbon-Containing Layers
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Method and System for Concurrent Computer Transaction Processing
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Graphics Controller Embedded in a Core Logic Unit
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Method for Providing Graphics Controller Embedded in a Core Logic Unit
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Mask Repattern Process
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Monolithic Inductance-Enhancing Integrated Circuits, Complementary Metal Oxide Semiconductor (Cmos) Inductance-Enhancing Integrated Circuits, Inductor Assemblies, and Inductance-Multiplying Methods
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System for Real-Time Control of Semiconductor Wafer Polishing
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Apparatus for Aligning Clock and Data Signals Received from a Ram
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Method for Aligning Clock and Data Signals Received from a Ram
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A Buffering Circuit Embedded in an Integrated Circuit Device Module Used for Buffering Clocks and Other Inputs Signals
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Method and Circuit for Self-Latching Data Read Lines in the Data Output Path of a Semiconductor Memory Device
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Electrical and Thermal Contact for Use in Semiconductor Devices
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Method for Fabricating Bga Package Using Substrate with Patterned Solder Mask Open in Die Attach Area
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Method of Fabricating a Dram Access Transistor with Dual Gate Oxide Technique
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Method to Prepare Hemi-Spherical Grain (Hsg) Silicon Using a Fluorine Based Gas Mixture and High Vacuum Anneal
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Testing and Burn-in of Ic Chips Using Radio Frequency Transmission
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Shallow Doped Junctions with a Variable Profile Gradation of Dopants
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Method of Making Straight Wall Containers and the Resultant Containers
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Low-Skew Differential Signal Converter
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Method and Apparatus for Testing Emissive Cathodes
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System Tour Generator
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Combination Mouse and Telephone Handset
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Drive Circuit with Over-Voltage Protection for Use with Pixel Cells and Other Circuits
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Addressing Scheme for a Double Data Rate Sdram
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Conductive Electrical Contacts, Capacitors, Drams, and Integrated Circuitry, and Methods of Forming Conductive Electrical Contacts, Capacitors, Drams and Integrated Circuitry
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Electrical Device Allowing for Increased Device Densities
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Correction of Field Effects in Photolithography
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Twin P-Well Cmos Imager
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Hermetically Sealed Chip Scale Packages Formed by Wafer Level Fabrication and Assembly
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Battery Electrolytes and Batteries
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Method for Controlling Pipelined Memory Access Requests
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Carcass-Tracking Apparatus Housings Carcass-Tracking Apparatus and Carcass-Tracking Methods
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Flash Memory with Overerase Protection
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Method of Programming Telephone Numbers and Identifiers in Multiple Databases
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Method of Programming Telephone Numbers and Identifiers in a Telephone
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Method of Programming Telephone Numbers and Identifiers in a Telephone
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Non-Volatile Data Storage Unit and Method of Controlling Same
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Dram with Intermediate Storage Cache and Separate Read and Write I/O
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Reduced Leakage Dram Storage Unit
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Multi-Layered Adhesive for Attaching a Semiconductor Die to a Substrate
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Latching Wordline Driver for Multi-Bank Memory
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Resputtering to Achieve Better Step Coverage
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Films Doped with Carbon for Use in Integrated Circuit Technology
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Polymer Based Circuit
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Method of Processing Semiconductive Material Wafers and Method of Forming Flip Chips and Semiconductor Chips
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Integrated Circuit with Temperature Detector
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Integrated Capacitor Bottom Electrode with Etch Stop Layer
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Power and Thermal Management Based on a Power Supply Output
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Thermal Management Apparatus Based on a Power Supply Output
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Method of Programming a Telephone
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Method for Multiplexing Bus Interfaces on a Computer Expansion Bus
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Multi-Bank Memory Input/Output Line Selection
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Hemispherical Grained Silicon on Conductive Nitride
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Memory Array Having a Multi-State Element and Method for Forming Such Array or Cellis Thereof
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Pulse-Controlled Light Emitting Diode Source
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Apparatuses for Electronic Identication of a Plurality of Passing Units and Methods of Electronic Identification of a Plurality of Passing Units
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Graphical Representation of System Information on a Remote Computer
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Method and Apparatus for Adaptively Adjusting the Timing of a Clock Signal Used to Latch Digital Signals, and Memory Device Using Same
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Apparatus for Configuring Devices on a Communications Channel
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Method of Configuring Devices on a Communications Channel
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Communications System and Method with a/D Converter
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Button-Type Batteries with an Insulating Jacket
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Memory Circuit with Switch for Selectively Connecting an Input/Output Pad Directly to a Nonvolatile Memory Cell
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Method of Fabricating a Dual Gate Dielectric
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Thin-Profile Battery Circuits and Constructions, Button-Type Battery Circuits and Constructions, Methods of Forming Thin-Profile Battery Circuits and Constructions, and Methods of Forming Button-Type Battery Circuits and Constructions
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Thin-Profile Battery Circuits and Constructions, Button-Type Battery Circuits and Constructions, Methods of Forming Thin-Profile Battery Circuits and Constructions, and Methods of Forming Button-Type Battery Circuits and Constructions
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Reference Voltage Generator Using Flash Memory Cells
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Methods of Forming Conductive Lines, Methods of Forming Antennas, Methods of Forming Wireless Communication Devices, Conductive Lines, Antennas, and Wireless Communications Devices
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Battery Mounting Apparatuses, Electronic Devices, and Methods of Forming Electrical Connections
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Wafer Level Burn-in of Memory Integrated Circuits
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Dual Mode Ddr Sdram/Sgram
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Enhancing Semiconductor Structure Surface Area Using Hsg and Etching
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Method for Interfacing Two Buses
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Conductive Container Structures Having a Dielectric Cap
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Laser Marking Techiques for Bare Semiconductor Die
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Bga Package Having Substrate with Patterned Solder Mask Defining Open Die Attach Area
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Thin Film Structure That May Be Used with an Adhesion Layer
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Interlaced Delay-Locked Loops for Controlling Memory-Circuit Timing
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Method and System for Accessing Rows in Multiple Memory Banks Within an Integrated Circuit
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Method and Apparatus for Generating a Phase Dependent Control Signal
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Capacitor/Antifuse Structure Having a Barrier-Layer Electrode and Improved Barrier Layer
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Capacitor/Antifuse Structure Having a Barrier-Layer Electrode and Improved Barrier Layer
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Microelectronic Devices, Methods of Operating Microelectronic Devices, and Methods of Providing Microelectronic Devices
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Dram Technology Compatible Processor/Memory Chips
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Capacitors and Dram Arrays
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Wireless Communication Systems, Interrogators and Methods of Communicating Within a Wireless Communication System
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Wireless Communication Systems, Interrogators and Methods of Communicating Within a Wireless Communication System
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Phase Shifters, Interrogators, Methods of Shifting a Phase Angle of a Signal, and Methods of Operating an Interrogator
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Multiple Operating System Quick Boot Utility
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Polishing Chucks, Semiconductor Wafer Polishing Chucks, Abrading Methods, Polishing Methods, Semiconductor Wafer Polishing Methods, and Methods of Forming Polishing Chucks
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Integrated Circuitry, Methods of Fabricating Integrated Circuitry, Methods of Forming Local Interconnects, and Methods of Forming Conductive Lines
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Button-Type Battery Constructions
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Increasing Readout Speed in Cmos Aps Sensors Through Block Readout
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Methods of Forming Thin-Profile Battery Electrode Connection Members, Button-Type Battery Electrode Connection Members, Thin-Profile Battery Constructions, and Button Type Battery Constructions, and Methods of Establishing Electrical Connections
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Low Skew Differential Receiver Disable Feature
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Method for Hot Adding a Network Adapter by Identifying and Executing the Adapter Driver Based Upon the Logical Board Number of the Network Adapter
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Integrated Circuitry, Dram Cells, Capacitors, and Methods of Forming Integrated Circuitry, Dram Cells and Capacitors
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Data Security for Digital Data Storage
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Data Security for Digital Data Storage
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Pre Test Electronic Mail Process
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Global Planarization Method and Apparatus
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Method for Chemical-Mechanical Planarization of Stop-on-Feature Semiconductor Wafers
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Bga Package and Method of Fabrication
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Memory Configuration Data Protection
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Charge Pump Circuit for Generating a Substrate Bias
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Synchronous Dram Modules Including Multiple Clock Out Signals for Increasing Processing Speed
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Synchronous Dram Modules Including Multiple Clock Out Signals for Increasing Processing Speed
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Method and System for Identifying and Configuring Peripheral Devices
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Flash Memory with Adjustable Write Operation Timing
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Circuit and Method for Refreshing Data Stored in a Memory Cell
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Electrochemical Cobalt Silicide Liner for Metal Contact Fills and Damascene Processes
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Digital Exposure Circuit for an Image Sensor
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Method of Wafer Level Chip Scale Packaging
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Apparatus for in-Situ Optical Endpointing on Web-Format Planarizing Machines in Mechanical or Chemical-Mechanical Planarization of Microelectronic-Device Substrate Assemblies and Methods for Making and Using Same
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Stacked Leads-Over Chip Multi-Chip Module
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Method of Improving Alignment Signal Strength by Reducing Refraction Index at Interface of Materials in Semiconductors
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Method of Improving Alignment Signal Strength by Reducing Refraction Index at Interface of Materials in Semiconductors
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Embedded Circuits
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System and Method for Locating Individuals and Equipment, Airline Reservation System, Communication System
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Range Finding Audio System
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On-Time Delivery, Tracking and Reporting
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Method for Fabricating an Array of Ultra-Small Pores for Chalcogenide Memory Cells
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Method for Fabricating an Array of Ultra-Small Pores for Chalcogenide Memory Cells
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Methods and Structures for Pad Reconfiguration to Allow Intermediate Testing During Manufacture of an Integrated Circuit
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Scalable High Dielectric Constant Capacitor
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Double Data Rate Synchronous Memory with Block-Write
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High Speed Programmable Counter
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Semiconductor-On-Insulator Transistor and Memory Circuitry Employing Semiconductor-on-Insulator Transistors
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Method of Facilitating the Selection of Features at Edges of Computer Touch Screens
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Synchronous Clock Generator Including a Delay-Locked Loop Signal Loss Detector
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Computer Touch Screen Adapted to Facilitate Selection of Features at Edge of Screen
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Communications System and Method with D/a Converter
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Integrated Circuitry, Methods of Fabricating Integrated Circuitry, Methods of Forming Local Interconnects, and Methods of Forming Conductive Lines
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Adjustable Output Driver Circuit
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Method for Fabricating Stackable Chip Scale Semiconductor Package
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Method and Apparatus for Generating an Internal Clock Signal That Is Synchronized to an External Clock Signal
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Semiconductor Device, Ball Grid Array Connection System, and Method of Making
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Synchronous Clock Generator Including a False Lock Detector
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Method of Making High Density Semiconductor Memory
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Crossbar Switch and Control for Data Networks Switching
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Routing Arbiter for Data Network Switching
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Integrated Circuit Memory Cell Having a Small Active Area and Method of Forming Same
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Method, Programmed Medium and System for Customizing Pre-Loaded Software
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Semiconductor Devices Having Gate Stack with Improved Sidewall Integrity
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Methods of Forming Capacitors, Dram Arrays, and Monolithic Integrated Circuits
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Methods of Forming Capacitors, Dram Arrays, and Monolithic Integrated Circuits
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Chemical Mechanical Polishing Methods
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Method and Apparatus for Detecting the Endpoint in Chemical-Mechanical Polishing of Semiconductor Wafers
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Method for Performing Analog Over-Program and Under-Program Detection for a Multistate Memory Cell
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Asymmetric, Double-Sided Self-Aligned Silicide and Method of Forming the Same
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Adjustable Output Driver Circuit
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Latching Wordline Driver for Multi-Bank Memory
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Method of Improving Copper Interconnects of Semiconductor Devices for Bonding
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Method and Structure for Reducing Contact Aspect Ratios
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Active Pixel Sensor with a Diagonal Active Area
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Wafer-Level Package and Methods of Fabricating
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Method and Apparatus for Using Photoemission to Determine the Endpoint of an Etch Process
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Method for Forming Batteries Comprising Polymeric Binder Material
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Thin Profile Electrode Connection Members and Button-Type Battery Electrode Connection Members
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Method of Etching a Substrate
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Integrated Circuit Having Aligned Fuses and Methods for Forming and Programming the Fuses
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Small Electrode for a Chalcogenide Switching Device and Method for Fabricating Same
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Methods for Electronic Tracking of Units Originating from a Common Source, and Assemblies Comprising Transponders Attached to Meat Spikes
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Clock Signal from an Adjustable Oscillator for an Integrated Circuit
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Right and Left Hand Circularly Polarized Rfid Backscatter Antenna
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Timing Circuit for High Speed Memory
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Mask Design Utilizing Dummy Features
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Method and Apparatus for a Detachable Interface Attachment Having a Memory Containing Device Information and Directly Routing Signals Through the Attachment
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Managing Redundant Electronic Messages
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Managing Redundant Electronic Messages
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Method and System for Managing Related Electronic Messages
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Battery-Powered Radio Frequency Communication Apparatus
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Method for Synchronizing Strobe and Data Signals from a Ram
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Apparatus for Synchronizing Strobe and Data Signals Received from a Ram
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Apparatus for Supporting Multiple Delayed Read Transactions Between Computer Buses
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Method for Supporting Multiple Delayed Read Transactions Between Computer Buses
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Capacitor/Antifuse Structure Having a Barrier-Layer Electrode and Improved Barrier Layer
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Capacitor/Antifuse Structure Having a Barrier-Layer Electrode and Improved Barrier Layer
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Apparatus and Method for Adjusting Clock Skew
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Films Doped with Carbon for Use in Integrated Circuit Technology
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Vertically Mountable Semiconductor Device, Assembly, and Methods
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Adjustable Delay Circuit for Setting the Speed Grade of a Semiconductor Device
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Reducing Internal Bus Speed in a Bus System Without Reducing Readout Rate
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Reconfigurable Memory with Selectable Error Correction Storage
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Methods of Forming Conductive Capacitor Plugs, Methods of Forming Capacitor Contact Openings, and Methods of Forming Memory Arrays
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Distributed Write Data Drivers for Burst Access Memories
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Adjustable Delay Circuit for Setting the Speed Grade of a Semiconductor Device
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System and Method for Regulating Data Capture in Response to Data Strobe Using Preamble, Postamble and Strobe Signature
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Reducing Memory Latency by Not Performing Bank Conflict Checks on Idle Banks
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Adjusting and Measuring the Timing of a Data Strobe Signal with a First Delay Line and Through Additional Delay Line Adapted to Receive Pulse Signal
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Wireless Communication Devices, Wireless Communication Systems, Communication Methods, Methods of Forming Radio Frequency Identification Devices, Methods of Testing Wireless Communication Operations, Radio Frequency Identification Devices, and Methods of Forming Ra
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Radio Frequency Identification Devices, Remote Communication Devices, Wireless Communication Systems, and Methods of Indicating Operation
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Method and Structure for Manufacturing Improved Yield Semiconductor Packaged Devices
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Multi-Bank Architecture for a Wide I/O Dram
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Method and Apparatus for Cleaning a Surface of a Microelectronic Substrate
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Output Data Path Having Selectable Data Rates
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Low Power, High Speed Level Shifter
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Rfid Material Tracking Method and Apparatus
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Method of Forming a Polysilicon Diode and Devices Incorporating Such Diode
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Modulated Spread Spectrum in Rf Identification Systems Method
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Integrated Circuit Memory Cell Having a Small Active Area and Method of Forming Same
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Devices for Sensing Changes in Environments Proximate the Devices, Devices for Sensing Termites, and Methods for Sensing Termites
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Devices for Sensing Changes in Environments Proximate the Devices, Devices for Sensing Termites, and Methods for Sensing Termites
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Devices for Sensing Living Organisms, Devices for Sensing Termites, Methods of Forming Devices for Sensing Termites, and Methods for Sensing Termites
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Memory Cell Incorporating a Chalcogenide Element
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Cmos Imager with Selectively Silicided Gates
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Apparatus Having Titanium Silicide and Titanium Formed by Chemical Vapor Deposition
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Methods of Forming a Contact Having Titanium Silicide and Titanium Formed by Chemical Vapor Deposition
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Methods of Forming a Contact Having Titanium Silicide Formed by Chemical Vapor Deposition
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Positioning Flowable Solder for Bonding Integrated Circuit Elements
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Interrogators, Wireless Communication Systems, Methods of Operating an Interrogator, Methods of Operating a Wireless Communication System, and Methods of Determining Range of a Remote Communication Device
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Interrogators, Wireless Communication Systems, Methods of Operating an Interrogator, Methods of Monitoring Movement of a Radio Frequency Identification Device, Methods of Monitoring Movement of a Remote Communication Device and Movement Monitoring Methods
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Rfid System in Communication with Vehicle on-Board Computer
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Lock in Pinned Photodiode Photodetector
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Method for Setting a Graphics Adapter Frequency in Response to a Battery Level
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Wireless Communications System and Method of Making
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Low Dielectric Constant Dielectric Films and Process for Making the Same
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Electrical Apparatuses, Termite Sensing Apparatuses, and Methods of Forming Electrical Apparatuses
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Electrical Apparatuses, Termite Sensing Apparatuses, Methods of Forming Electrical Apparatuses, and Methods of Sensing Termites
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Tamper Resistant Smart Card and Method of Protecting Data in a Smart Card
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Capacitor Structures with Recessed Hemispherical Grain Silicon
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Web-Format Planarizing Machines and Methods for Planarizing Microelectronic Substrate Assemblies
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Method of Storing a Temperature Threshold in an Integrated Circuit, Method of Modifying Operation of Dynamic Random Access Memory in Response to Temperature, Programmable Temperature Sensing Circuit and Memory Integrated Circuit
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Method and Apparatus for Trench Isolation Process with Pad Gate and Trench Edge Spacer Elimination
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Fuse Option for Multiple Logic Families on the Same Die
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Method and Apparatus for Supporting a Polishing Pad During Chemical-Mechanical Planarization of Microelectronic Substrates
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Wafer Level Fabrication and Assembly of Chip Scale Packages
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Method and Apparatus for High-Speed Edge-Programmable Timing Signal Generator
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Capacitors Having a Capacitor Dielectric Layer Comprising a Metal Oxide Having Multiple Different Metals Bonded with Oxygen
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Method for Writing to Multiple Banks of a Memory Device
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Under Bump Metalization Pad and Solder Bump Connections
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Semiconductor Devices Having Mirrored Terminal Arrangements, Devices Including Same, and Methods of Testing Such Semiconductor Devices
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Transponder Modules, Rf Tagging System, Method of Operating a Transponder Module and Methods of Tagging an Object Having a Conductive Surface
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Semiconductor Structure and Apparatus Having Separated Polysilicon Grains
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Double Data Rate Scheme for Data Output
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Method and Apparatus for Programmable Control Signal Generation for a Semiconductor Device
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Output Circuit for a Double Data Rate Dynamic Random Access Memory, Double Data Rate Dynamic Random Access Memory, Method of Clocking Data Out from a Double Data Rate Dynamic Random Access Memory and Method of Providing a Data Strobe Signal
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Remote Communication Devices, Radio Frequency Identification Devices, Wireless Communication Systems, Wireless Communication Methods, Radio Frequency Identification Device Communication Methods, and Methods of Forming a Remote Communication Device
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Apparatus Having a Titanium Alloy Layer
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Method of Manufacturing and Testing an Electronic Device, and an Electronic Device
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Epoxy, Epoxy System, and Method of Forming a Conductive Adhesive Connection
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Method of Manufacturing and Testing an Electronic Device, and an Electronic Device
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Method of Improving Alignment Signal Strength by Reducing Refraction Index at Interface of Materials in Semiconductors
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Method for Resolving Signals Collisions Between Multiple Rfid Transponders in a Field
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Reduced Leakage Dram Storage Unit
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Stacked Leads-Over-Chip Multi-Chip Module
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Digital Clock Recovery Loop
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Stacked Leads-Over Chip Multi-Chip Module
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Method of Bonding a Flexible Polymer Tape to a Substrate to Reduce Stresses on the Electrical Connections
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Method and Apparatus Employing External Light Source for Endpoint Detection
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Z-Axis Electrical Contact for Microelectric Devices
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Polishing Chucks, Semiconductor Wafer Polishing Chucks, Abrading Methods, Polishing Methods, Semiconductor Wafer Polishing Methods, and Methods of Forming Polishing Chucks
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Recessed-Container Cells and Method of Forming the Same
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E-Mail Virus Detection Utility
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Method for Automatically Retrieving and Installing Device Drivers Across a Network
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Dram Capacitor Formulation Using a Double-Sided Electrode
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Stackable Ball Grid Array Package
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Vertically Mountable and Alignable Semiconductor Device, Assembly, and Methods
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Vertically Mountable Interposer, Assembly and Method
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System for Redirecting I/O Device Configuration Information to Memory for Identification of Data Storage Devices
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Micro Power Micro-Sized Cmos Active Pixel
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Methods of Fixturing a Flexible Substrate and a Processing Carrier and Methods of Processing a Flexible Substrate
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Memory Cell Having a Reduced Active Area and a Memory Array Incorporating the Same
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A Memory Cell Having a Reduced Active Area and a Memory Array Incorporating the Same
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Reduced Leakage Dram Storage Unit
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Multi-Chip Stacked Devices
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Methods of Forming Thin-Profile Battery Circuits and Constructions, and Methods of Forming Button-Type Battery Circuits and Constructions
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Methods of Forming Electrically Conductive Interconnections and Electrically Interconnected Substrates
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Methods for Forming Electrically Conductive Interconnections and Electrically Interconnected Substrates
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Electrical Apparatuses, Methods of Forming Electrical Apparatuses, and Termite Sensing Methods
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Pipelined Packet-Oriented Memory System Having a Unidirectional Command and Address Bus and a Bidirectional Data Bus
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Pipelined Packet-Oriented Memory System Having a Undirectional Command and Address Bus and a Bidirectional Data Bus
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Plural Pipelinedpacket-Oriented Memory Systems Having a Unidirectional Command and Address Bus and a Bidirectional Data Bus
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Pipelined Packet-Oriented Memory System Having a Unidirectional Command and Address Bus and a Bidirectional Data Bus
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Button Cell Constructions and Thin Profile Battery Constructions
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Pipelined Packet-Oriented Memory System Having a Unidirectional Command and Address Bus and a Bidirectional Data Bus
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Thin Profile Batteries
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In-Sheet Teansceiver Testing
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Semiconductor Wafer for Improved Chemical-Mechanical Polishing Over Large Area Features
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Twin Well Methods of Forming Cmos Integrated Circuitry
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Semiconductor Processing Methods of Forming Stacked Capacitors
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Communications System and Method, Fleet Management System and Method, and Method of Impeding Theft of Fuel
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System for Real-Time Control of Semiconductor Wafer Polishing
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Method and Apparatus for Local Control Signal Generation in a Memory Device
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Two Step Memory Device Command Buffer Apparatus and Method and Memory Devices and Computer Systems Using Same
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Method and Apparatus for Mechanical and Chemical-Mechanical Planarization of Microelectronic Substrates
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Testing Parameters of an Electronic Device
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Apparatus and Method for Selecting Data Bits Read from a Multistate Memory
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Processing Methods of Forming Integrated Circuitry Memory Devices, Methods of Forming Dram Arrays, and Related Semiconductor Masks
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Packages for Semiconductor Die
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Communication Devices, a Radio Frequency Identification Device, and Methods of Communicating
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Display of System Information
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Thin-Profile Battery Circuits and Constructions, Button-Type Battery Circuits and Constructions, Methods of Forming Thin-Profile Battery Circuits and Constructions, and Methods of Forming Button-Type Battery Circuits and Constructions
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Wireless Communication Devices and Methods of Forming Wireless Communication Devices
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Mask Repattern Process
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Method of Forming Cmos Integrated Circuitry
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Center Bond Flip Chip Semiconductor Carrier and a Method of Making and Using It
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Contoured Surface Cover Plate for Image Sensor Array
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Die Attach Material for Tbga or Flexible Circuitry
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Vertically Mountable Semiconductor Device and Methods
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Apparatus and Method for Reducing Removal Forces for Cmp Pads
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Method and Apparatus for Transferring Test Data from a Memory Array
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Thin Profile Battery Bonding Method, Method of Conductively Interconnecting Electronic Components, Battery Powerable Apparatus, Radio Frequency Communication Device, and Electric Circuit
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Method of Increasing Capacitance of Memory Cells Incorporating Hemispherical Grained Silicon
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Electrically Powered Postage Stamp or Mailing or Shipping Label Operative with Radio Frequency (Rf) Communication
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Method of Fabricating and Testing an Embedded Semiconductor Device
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Embedded dram architecture with local data drivers and programmable number of data read and data write lines
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Flip Chip Adaptor Package For Bare Die
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Metal Oxynitride Capacitor Barrier Layer
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Split embedded dram processor
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Wireless Identification Device, Rfid Device, and Method of Manufacturing Wireless Identification Device
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Chemical vapor deposition of titanium
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Applying Epitaxial Silicon in Disposable Spacer Flow
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Architecture and package orientation for high speed memory devices
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Fast accessing of a memory device
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Semiconductor-On-Insulator Transistor, Memory Circuitry Employing Semiconductor-on-Insulator Transistors, Method of Forming a Semiconductor-on-Insulator Transistor, and Method of Forming Memory Circuitry Employing Semiconductor-on-Insulator Transistors
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Structurally-Stabilized Capacitors and Method of Making of Same
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Memory System, Method and Predecoding Circuit Operable in Different Modes for Selectively Accessing Multiple Blocks of Memory Cells for Simultaneous Writing or Erasure
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Method and apparatus for setting write latency
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System for real-time control of semiconductor wafer polishing
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Method of Speeding Power-Up of an Amplifier,and Amplifier
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Radio Frequency Data Communications Device
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Write scheme for a double data rate sdram
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Vertical surface mount assembly and methods
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Vertical surface mount assembly and methods
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Method and apparatus for detecting the endpoint in chemical-mechanical polishing of semiconductor wafers
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Methods of insulating a thin-profile battery
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Digit line architecture for dynamic memory
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Digit line architecture for dynamic memory
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Protective Conformal Silicon Nitride Films and Spacers
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Method and apparatus for spacing apart panels in flat panel displays
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Improved Data Output Buffer
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System and Method to Reduce Cycle Time by Performing Column Redundancy Checks During a Delay to Accomodate Variations in Timing of a Data Strobe Signal
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System Supporting Multiple Memory Modes Including a Burst Extended Data Out Mode
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Polishing chucks,semiconductor wafer polishing chucks, abrading methods, polishing methods, semiconductor wafer polishing methods, and methods of forming polishing chucks
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Communication devices, radio frequency identification devices, methods of forming a communication device, and methods of forming a radio frequency identification device
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Method to Form Hemispherical Grained Polysilicon
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Methods of forming flip chip bumps and related flip chip bump Constructions
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Methods of Forming Electrically Conductive Interconnections and Electrically Interconnected Substrates
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Portable Computer with Low Power Cd-Player Mode
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Methods of Insulating Batteries, Thin-Profile Batteries, and Button-Type Batteries, and Battery Constructions
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Method of Controlling Access to a Movable Container and to a Compartment of a Vehicle, and a Secure Cargo Transportation System
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Backend Metallization Method and Device Obtained Therefrom
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Inductor formed at least partially in a substrate
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Thin-Profile Battery Circuits and Constructions, Button-Type Battery Circuits and Constructions
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Integrated Circuit Inductor with a Magnetic Core
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Wireless Communication Devices, Radio Frequency Identification Devices, Methods of Forming a Wireless Communication Device, and Methods of Forming a Radio Frequency Identification Device
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Radio Frequency-Transmissive Compositions, Methods of Forming Radio Frequency-Transmissive Compositions, Microelectronic Devices, Wireless Radio Frequency Communication Devices, and Methods of Forming Microelectronic Devices, Wireless Radio Frequency Communication
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Capacitor over bit line memory cell and process
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Method and Apparatus for Controlling Reproduction of an Audiovisual Work
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Computer System Having Memory Device with Adjustable Data Clocking Using Pass Gates
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Synchronous Memory Device Having an Adjustable Data Clocking Circuit
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Semiconductor Processing Methods of Removing Conductive Material
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Semiconductor Package Including Flex Circuit, Interconnects and Dense Array External Contacts
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Method for fabricating floating gate semiconductor devices with trench isolation structures and self aligned floating gates
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Method for Fabricating a Floating Gate Semiconductor Device
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Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors
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Stackable ball grid array package
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Global planarization method and apparatus
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Low Dielectric Constant Dielectric Films and Process for Making the Same
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Radio frequency data communications device
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Method of Manufacturing an Enclosed Transceiver
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Radio Frequency Antenna with Current Controlled Sensitivity
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Method for Surface Mounting Electrical Components to a Substrate
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Method for Producing Improved Microelectronic Contacts
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Method for writing to multiple banks of a memory device
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Bga Package and Method of Fabrication
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Method of forming a polysilicon diode and devices incorporating such diode
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Reduced leakage dram storage unit
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Radio frequency data communications device
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Method of addressing messages, and establishing communications using a tree search technique that skips levwls
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Monolithic Inductance-Enhancing Integrated Circuits, Complementary Metal Oxide Semiconductor (Cmos) Inductance-Enhancing Integrated Circuits, Inductor Assemblies, and Inductance-Multiplying Methods
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System for Facilitating the Replacement or Insertion of Devices in a Computer System Through the Use of a Graphical User Interface
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Tamper resistant smart card and method of protecting data in a smart card
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Method of addressing messages and communications system
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Drive Circuit with Over-Voltage Protection for Use with Pixel Cells and Other Circuits
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Automated Antenna Trim for Transmitting and Receiving Semiconductor Devices
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Field Emission Tips and Methods for Fabricating the Same
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Method for Designing Photolithographic Reticle Layout, Reticle, and Photolithographic Process
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Apparatus for improving the performance of a temperature-sensitive etch
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Method for protecting an integrated circuit during burn-in testing
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Method and Apparatus for Facilitating Purchase Transactions Across a Network
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Method for Signal Processing
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Structure and method for improved signal processing
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Apparatus for reading state of multistate non-volatile memory cells
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Dram content addressable memory using part of the content as an address
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Circuit and method for refreshing data stored in a memory cell
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Flash with Consistent Latency for Read Operations
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Predictive Timing Calibration for Memory Devices
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Stage having controlled variable resistance load circuit for use in voltage controlled ring oscillator
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Timing Calibration Pattern for Sldram
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Electrical and thermal contact for use in semiconductor devices
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Elimination of precharge operation in synchronous flash memory
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Radio Frquency Identification Device and Methods of Determining a Communication Range of an Interrogator of a Wireless Identification System
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Semiconductor Memory Implementing Internally Generated Commands
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Method for Communicating a Software-Generated Pulse Waveform Between Two Servers in a Network
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Asymmetric, Double-Sided Self-Aligned Silicide
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Wireless communication packages, a radio frequency identification device communication package, an appendage, a method of communicating, and a method of forming a wireless communication package
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Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry
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Method of Making Straight Wall Containers and the Resultant Containers
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Wireless communication devices and methods of forming wireless communication devices
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Method and apparatus for planarizing and cleaning microelectronic substrates
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Polishing Chucks, Semiconductor Wafer Polishing Chucks, Abrading Methods, Polishing Methods, Semiconductor Wafer Polishing Methods, and Methods of Forming Polishing Chucks
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Method of Remote Access and Control of Environmental Conditions
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Programmable Multiple Texture Combine Circuit for a Graphics Processing System and Method for Use Thereof
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Capacitor/Antifuse Structure Having a Barrier-Layer Electrode and Improved Barrier Layer
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Hemispherical Grained Silicon on Conductive Nitride
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Memory System That Sets a Predetermined Phase Relationship Between Read and Write Clock Signals at a Bus Midpoint for a Plurality of Spaced Device Locations
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Image Sensor Packaging with Package Cavity Sealed by the Imaging Optics
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Frequency Doubler and Method of Doubling Frequency
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Electrochemical Cobalt Silicide Liner for Metal Contact Fills and Damascene Processes
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Method and System for Accessing Rows in Multiple Memory Banks Within an Integrated Circuit
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Capture Clock Generator Using Master and Slave Delay Locked Loops
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Output Circuit for a Double Data Rate Dynamic Random Access Memory, Double Data Rate Dynamic Random Access Memory, Method of Clocking Data Out from a Double Data Rate Dynamic Random Access Memory and Method of Providing a Data Strobe Signal
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Radio Frequency-Transmissive Compositions, Methods of Forming Radio Frequency-Transmissive Compositions, Microelectronic Devices, Wireless Radio Frequency Communication Devices, and Methods of Forming Microelectronic Devices, Wireless Radio Frequency Communication
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Wireless Communication System, Radio Frequency Communications System, Wireless Communications Method, Radio Frequency Communications Method, and Backscatter Radio Frequency Communications System
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Semiconductor Devices Having Mirrored Terminal Arrangements, Devices Including Same, and Methods of Testing Such Semiconductor Devices
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Epoxy, Epoxy System, and Method of Forming a Conductive Adhesive Connection
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Methods and Apparatuses for Mechanical and Chemical-Mechanical Planarization of Microelectronic-Device Substrate Assemblies on Planarizing Pads
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Methods and Apparatuses for Mechanical and Chemical-Mechanical Planarization of Microelectronic-Device Substrate Assemblies on Planarizing Pads
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Methods and Apparatuses for Mechanical and Chemical-Mechanical Planarization of Microelectronic-Device Substrate Assemblies on Planarizing Pads
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Phase Splitter Using Digital Delay Locked Loops
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Circut Having a Controllable Slew Rate
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Electrical and Thermal Contact for Use in Semiconductor Devices
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An Apparatus Comprising a Translation Lookaside Buffer for Graphics Address Remapping of a Virtual Addresses
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Lock in Pinned Photodiode Photodetector
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Large-Area Fed Apparatus and Method for Making Same
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Methods of Forming Transistor Gates; and Methods of Forming Programmable Read-Only Memory Constructions
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Two Stage Transfer Molding Method to Encapsulate Mmc Module
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Dual Gate Dielectric Construction
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256 Meg Dynamic Random Access Memory
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Integrated Circuit Memory Cell Having a Small Active Area and Method of Forming Same
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Method and apparatus for high-speed edge-programmable timing signal generation
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256 meg dynamic random access memory
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Stacked Mass Storage Flash Memory Package
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Metal Gate Engineering for Surface P-Channel Devices
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Voltage Generator Stability Indicator Circuit
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256 Meg Dynamic Random Access Memory
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Method and System for Adjusting the Timing Offset Between a Clock Signal and Respective Digital Signals Transmitted Along with That Clock Signal, and Memory Device and Computer System Using Same
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Reducing Memory Latency by Not Performing Bank Conflict Checks on Idle Banks
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256 Meg Dynamic Random Access Memory
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Small Electrode for Chalcogenide Memories
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256 Meg Dynamic Random Access Memeory
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Three Dimensional Rendering Including Motion Sorting
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Capacitor with High Dielectric Constant Materials and Method of Making
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256 Meg Dynamic Random Access Memory
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Optimized Flash Memory Cell
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256 Meg Dynamic Random Access Memory
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Flip Chip Adaptor Package for Bare Die
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Structure for Reducing Contact Aspect Ratios
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Atomic Layer Deposition of Capacitor Dielectric
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Spin Coating for Maximum Fill Characteristic Yielding a Planarized Thin Film Surface
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Spin Coating for Maximum Fill Characteristic Yielding a Planarized Thin Film Surface
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Active Termination Circuit and Method for Controlling the Impedance of External Integrated Circuit Terminals
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Low Pass Filters in Dll Circuits
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Metal Oxynitride Capacitor Barrier Layer
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Metal Oxynitride Capacitor Barrier Layer
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Metal Oxynitride Capacitor Barrier Layer
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Program Controlled Embedded-Dram-Dsp Architecture and Methods
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Stacked Chip Connection Using Stand Off Stitch Bonding
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Methods of Determining a Communications Range of an Interrogator of a Wireless Identification System and Methods of Verifying Operation of a Wireless Identification System
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Method of Fabricating a Dram Transistor with a Dual Gate Oxide Technique
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Sequential Nibble Burst Ordering for Data
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Method for Manufacturing Tapered Openings Using an Anisotropic Etch During the Formation of a Semiconductor Device
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Virtual Shadow Registers and Virtual Register Windows
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Method and Architecture to Calibrate Read Operations in Synchronous Flash Memory
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Optimized Container Stacked Capacitor Dram Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing
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Block Write Circuit and Method for Wide Data Path Memory Devices
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Multi-Mode Synchronouos Memory Device and Method of Operating and Testing Same
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Flip-Chip with Matched Signal Lines, Ground Plane and Ground Bumps Adjacent Signal Bumps
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Memory Device Operable in Either a High-Power, Full-Page Size Mode or a Low-Power, Reduced-Page Size Mode
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Method and Structure for Manufacturing Improved Yield Semiconductor Packaged Devices
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Producing Walking One Pattern in Shift Register
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Method to Alter Chalcogenide Glass for Improved Switching Characteristics
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Mim Capacitor with Metal Nitride Electrode Materials and Method of Formation
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Memory Device Having a Relatively Wide Data Bus
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Computer Touch Screen Adapted to Facilitate Selection of Features at Edge of Screen
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Bond Pad Rerouting Element, Rerouted Semiconductor Devices Including the Rerouting Element, and Assemblies Including the Rerouted Semiconductor Devices
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Semiconductor Device, Ball Grid Array Connection System, and Method of Making
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Feedback Stabilized Light Source with Rail Control
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Method for Designing Photolithographic Reticle Layout, Reticle, and Photolithographic Process
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Radio Frequency Data Communications Device
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Field Emission Tips and Methods for Fabricating the Same
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256 Meg Dynamic Random Access Memory
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Method for Digit Line Architecture for Dynamic Memory
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Dual Floating Gate Programmable Read Only Memory Cell Structure and Method for Its Fabrication and Operation
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Programable Identification Circuitry
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Synchronous Memory Open Page Register
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Non-Volatile Delay Register
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Low Current Wide Vref Range Input Buffer
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Atomic Layer Deposition Method
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Sealed Electronic Device Packages with Transparent Coverings
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Co-Sputter Deposition of Metal-Doped Chalcogenides
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Capacitor structure with high dielectric constant materials
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Method and Unit for Selectively Enabling an Input Buffer Based on an Indication of a Clock Transition
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Apparatus for Automatically Retrieving and Installing Device Drivers Across a Network
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Multi-Match Detection Circuit for Use with Content-Addressable Memories
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Controllable Ovonic Phase-Change Semiconductor Memory Device
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Dynamically Setting Burst Length of Memory Device by Applying Signal to at Least One External Pin During a Read or Write Transaction
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Dram Technology Compatible Processor/Memory Chips
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Dram Technology Compatible Processor/Memory Chips
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Dram Technology Compatible Processor/Memory Chips
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Method for forming standard voltage threshold and low voltage threshold MOSFET devices
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Method of Making High Density Semiconductor Memory
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Flip-Chip with Matched Lines and Ground Plane
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Method for Fabricating a Floating Gate Semiconductor Device
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Applying Epitaxial Silicon in Disposable Spacer Flow
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Methods of Encapsulating Selected Locations of a Semiconductor Die Assembly Using a Thick Solder Mask
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Low-Loss Coplanar Waveguides and Method of Fabrication
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Digital Dual-Loop Dll Design Using Coarse and Fine Loops
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Double Ldd Devices for Improved Dram Refresh
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A Circuit for Adjusting a Self-Refresh Rate to Maintain Dynamic Data at Low Supply Voltages
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Memory Device and Computer System Including Circuit for Adjusting a Self-Refresh Rate to Maintain Dynamic Data at Low Supply Voltages
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Non-Continuous Conductive Layer for Laminated Substrates
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Two-Stage Transfer Molding Method to Encapsulate Mmc Module
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Fast Accessing of a Memory Device Using Decoded Address During Setup Time
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Battery-Powered Test-Configured Electronic Device with Test-Contact Extensions
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Method of Synchronizing Read Timing in a High Speed Memory System
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Write Data Masking for Higher Speed Drams
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High Density Dynamic Ternary-Cam Memory Architecture
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Non-Contiguous Address Erasable Blocks and Command in Flash Memory
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Synchronous Memory with Open Page
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Flash Memory with Multiple Status Reading Capability
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Flash Memory with Multiple Status Reading Capability
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Measure Controlled Delay with Duty Cycle Control
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Split Word Line Ternary Cam Architecture
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Dram Power Bus Control
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Power Savings in Active Standby Mode
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Increasing Drive Strength and Reducing Propagation Delays Through the Use of Feedback
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Modified Persistent Auto Precharge Command Protocol System and Method for Memory Devices
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Zero Power Chip Standby Mode
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Enhanced Atomic Layer Deposition
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Films Doped with Carbon for Use in Integrated Circuit Technology
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Rfid Material Tracking Method and Apparatus
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Rfid Material Tracking Method and Apparatus
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Rfid Material Tracking Method and Apparatus
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Rfid Material Tracking Method and Apparatus
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System for Determining Status of Multiple Interlocking Fifo Buffer Structures Based on the Position of at Least One Pointer of Each of the Multiple Buffers
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Connected Support Entitlement System and Method of Operation
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Rfid Material Tracking Method and Apparatus
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Zero Power Chip Standby Mode
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Method and Apparatus for Setting and Compensating Read Latency in a High Speed Dram
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Method and Apparatus for Chemically, Mechanically, and/or Electrolytically Removing Material from Microelectronic Substrates
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Reduced Current Input Buffer Circuit
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Flip-Chip Image Sensor Packages and Methods of Fabrication
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Measure-Controlled Delay Circuit with Reduced Playback Error
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Delay Lock Loop Circuit Useful in a Synchronous System and Associated Methods
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Method for Forming Conductive Material in Opening and Structures Regarding Same
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Methods and Apparatus for Electromechanically and/or Electrochemically-Mechanically Removing Conductive Material from a Microelectronic Substrate
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Power Reduction for Delay Locked Loop Circuits
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Method of Controlling a Delay Locked Loop
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Controller for Delay Locked Loop Circuits
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Distributed Write Data Drivers for Burst Access Memories
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Semiconductor Package Including Flex Circuit, Interconnects and Dense Array External Contacts
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In-Situ Chemical-Mechanical Planarization Pad Metrology Using Ultrasonic Imaging
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Distributed Write Data Drivers for Burst Access Memories
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Multi-Bank Memory Accesses Using Posted Writes
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Method and System for Controlling Memory Accesses to Memory Modules Having a Memory Hub Architecture
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Digit Line Architecture for Dynamic Memory
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Zero Power Chip Standby Mode
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Distributed Write Data Drivers for Burst Access Memories
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Full-Scene Anti-Aliasing Method and System
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Capacitor Structures with Dual-Sided Electrode
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Structure for Reducing Contact Aspect Ratios
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Structure for Reducing Contact Aspect Ratios
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Electrical Device Allowing for Increased Device Densities
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Electrical Device Allowing for Increased Device Densities
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256 Meg Dynamic Random Access Memory
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Method and Circuit for Adjusting the Timing of Output Data Based on an Operational Mode of Output Drivers
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Power Validation for Memory Devices on Power Up
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Flash Memory Circuitry
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Method for Making Large-Area Fed Apparatus
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Non-Volatile Memory Device with Erase Address Register
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Non-Volatile Memory Device with Erase Address Register
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Non-Volatile Memory Device with Erase Address Register
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Atomic Layer Deposition Methods and Atomic Layer Deposition Tools
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Methods of Forming Conductive Through-Wafer Vias
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Variable Delay Circuit and Method, and Delay Locked Loop, Memory Device and Computer System Using Same
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Method and Apparatus for Generating Expect Data from a Captured Bit Pattern, and Memory Device Using Same
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Burst Read Addressing in a Non-Volatile Memory Device
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Burst Read Addressing in a Non-Volatile Memory Device
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Method and Apparatus for Independent Output Driver Calibration
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Variable Delay Circuit and Method, and Delay Locked Loop, Memory Device and Computer System Using Same
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Variable Delay Circuit and Method, and Delay Locked Loop, Memory Device and Computer System Using Same
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Method of Fabricating a Wireless Radio Frequency Identification Device
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Methods of Electrically Contacting to Conductive Plugs, Methods of Forming Contact Openings, and Methods of Forming Dynamic Random Access Memory Circuitry
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Structure for Contact Formation Using a Silicon-Germanium Alloy
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Method of Forming Minimally Spaced Word Lines
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Memory Device and Method Having Data Path with Multiple Prefetch I/O Configurations
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Memory Device and Method Having Data Path with Multiple Prefetch I/O Configurations
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Memory Device and Method Having Data Path with Multiple Prefetch I/O Configurations
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Memory Device and Method Having Data Path with Multiple Prefetch I/O Configurations
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Method of Fabricating a Small Electrode for Chalcogenide Memory Cells
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Semiconductor Device with Self Refresh Test Mode
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Refresh Controller and Address Remapping Circuit and Method for Dual Mode Full/Reduced Density Drams
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Thin Film Structure That May Be Used with an Adhesion Layer
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Method of Forming a Mim Capacitor with Metal Nitride Electrode
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Solder Ball Landpad Design to Improve Laminate Performance
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Programmable Dual-Drive Strength Output Buffer with a Shared Boot Circuit
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Nand Flash Memory with Improved Read and Verification Threshold Uniformity
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Magnitude Comparator Based Content Addressable Memory for Search and Sorting
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Semiconductor Device Having Integrated Circuit Contact
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Assemblies Including Stacked Semiconductor Devices Separated a Distance Defined by Adhesive Material Interposed Therebetween, Packages Including the Assemblies, and Methods
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Lock in Pinned Photodiode Photodetector
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Memory Module and Method Having Improved Signal Routing Topology
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Dynamic Synchronization of Data Capture on an Optical or Other High Speed Communications Link
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Memory Hub and Access Method Having Internal Prefetch Buffers
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Posted Write Buffers and Methods of Posting Write Requests in Memory Modules
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Methods of Forming Memory Cells Having Self-Aligned Silicide
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Bottom Antireflection Coating Color Filter Process for Fabricating Solid State Image Sensors
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Memory Device Having Data Paths with Multiple Speeds
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Circuit Substrates, Semiconductor Packages, and Ball Grid Arrays
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Flip-Chip Image Sensor Packages and Methods of Fabrication
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Method of Forming Minimally Spaced Word Lines
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Cmos Imager with Selectively Silicided Gate
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Digit Line Architecture for Dynamic Memory
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Planarizing Machines and Control Systems for Mechanical and/or Chemical-Mechanical Planarization of Microelectronic Substrates
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Controllable Ovonic Phase-Change Semiconductor Memory Device
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Clamping Circuit for the Vpop Voltage Used to Program Antifuses
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Delay Lock Loop Circuit Useful in a Synchronous System and Associated Methods
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Interleaved Delay Line for Phase Locked and Delay Locked Loops
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Portable Computer Supporting Paging Instructions
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Burst Write in a Non-Volatile Memory Device
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Ddr Ii Write Data Capture Calibration
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Multi-Match Detection Circuit for Use with Content-Addressable Memories
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Method and System for Low Power Refresh of Dynamic Random Access Memories
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Semiconductor Package Having Flex Circuit with External Contacts
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Method of Forming a Structure Over a Semiconductor Substrate
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Fet Having Epitaxial Silicon Growth
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Low-Loss Coplanar Waveguides and Method of Fabrication
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Wireless Identification Device, Rfid Device with Push-on/Push Off Switch, and Method of Manufacturing Wireless Identification Device
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Active Termination Circuit and Method for Controlling the Impedance of External Integrated Circuit Terminals
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Resistance Variable Memory Elements Based on Polarized Silver-Selenide Network Growth
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Row Driver for Selectively Supplying Operating Power to Imager Pixel
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Method of Timing Calibration Using Slower Data Rate Pattern
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Methods for Forming Assemblies and Packages That Include Stacked Semiconductor Devices Separated a Distance Defined by Adhesive Material Interposed Therebetween
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Fast and Compact Circuit for Bus Inversion
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Data Amplifier Having Reduced Data Lines and/or Higher Data Rates
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Dynamic Command and/or Address Mirroring System and Method for Memory Modules
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Interpolator for a Cmos Image Sensor Using a Digital Register
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Accelerated Graphics Port for a Multiple Memory Controller Computer System
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Method of Synchronizing Read Timing in a High Speed Memory System
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Sequential Nibble Burst Ordering for Data
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Zero Latency-Zero Bus Turnaround Synchronous Flash Memory
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Method for Fabricating an Array of Ultra-Small Pores for Chalcogenide Memory Cells
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User Selectable Banks for Dram
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Structure for Contact Formation Using a Silicon-Germanium Alloy
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Methods and Apparatuses for Electrochemical-Mechanical Polishing
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Multi-Function Floating Point Arithmetic Pipeline
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Synchronous Flash Memory Emulating the Pin Configruation of Sdram
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Synchronous Flash Memory with Concurrent Write and Read Operation
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Opitmized Flash Memory Cell
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Semiconductor Isolator System
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Thin Profile Battery Bonding Method, Method of Conductively Interconnecting Electronic Components, Battery Powerable Apparatus, Radio Frequency Communication Device, and Electric Circuit
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Method and Architecture to Calibrate Read Operations in Synchronous Flash Memory
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Semiconductor Fabrication Using a Collar
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System and Method for Communicating Information to a Memory Device Using a Reconfigured Device Pin
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Films Doped with Carbon for Use in Integrated Circuit Technology
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Remote Communication Devices, Radio Frequency Identification Devices, Wireless Communication Systems, Wireless Communication Methods, Radio Frequency Identification Device Communication Methods, and Methods of Forming a Remote Communication Device
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Method of Improving Copper Interconnects of Semiconductor Devices for Bonding
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Two-Stage Transfer Molding Device to Encapsulate Mmc Module
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Methods of Operating Microelectronic Devices, and Methods of Providing Microelectronic Devices
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Capacitive Multidrop Bus Compensation
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Method and Apparatus for Achieving Low Power Consumption During Power Down
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Synchronous Flash Memory with Accessible Page During Write
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Method of Forming Shallow Doped Junctions Having a Variable Profile Gradation of Dopants
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Method of Forming a Non-Continuous Conductive Layer for Laminated Substrates
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Status Register to Improve Initialization of a Synchronous Memory
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Method of Providing an Interface to a Plurality of Peripheral Devices Using Bus Adapter Chips
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Multiple Operating System Quick Boot Utility
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Methods and Apparatuses for Mechanical and Chemical-Mechanical Planarization of Microelectronic-Device Substrate Assemblies on Planarizing Pads
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Memory Hub and Method for Providing Memory Sequencing Hints
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Method and System for Using Dynamic Random Access Memory as Cache Memory
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Reduced Power Registered Memory Module and Method
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Phase Detector and Method Having Hysteresis Characteristics
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Memory Modules Having Accurate Operating Current Values Stored Thereon and Methods for Fabricating and Implementing Such Devices
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Burst Read Addressing in a Non-Volatile Memory Device
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Processing Memory Requests in a Pipelined Memory Controller
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Synchronous Flash Memory with Status Burst Output
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Memory Device Having Different Burst Order Addressing for Read and Write Operations
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High Density Dynamic Ternary-Cam Memory Architecture
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Wireless Communication Devices, Radio Frequency Identification Devices, Radio Frequency Identification Device Communication Systems, Wireless Communication Methods, and Radio Frequency Identification Device Communication Methods
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Formation of Standard Voltage Threshold and Low Voltage Threshold Mosfet Devices
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Clamping Circuit for the Vpop Voltage Used to Program Antifuses
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Web-Format Polishing Pads and Methods for Manufacturing and Using Web-Format Polishing Pads in Mechanical and Chemical-Mechanical Planarization of Microelectronic Substrates
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Flash Memory Architecture for Optimizing Performance of Memory Having Multi-Level Memory Cells
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Automated Antenna Trim for Transmitting and Receiving Semiconductor Devices
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Detecting "Almost Match" in a Cam
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In-Situ Chemical-Mechanical Planarization Pad Metrology Using Ultrasonic Imaging
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Structurally-Stabilized Capacitors and Method of Making of Same
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Increasing Readout Speed in Cmos Aps Sensors Through Block Readout
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Programmable Dual Drive Strength Output Buffer with a Shared Boot Circuit
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Transfer Mold Semiconductor Packaging Processes
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Integrated Circuit Inductor with a Magnetic Core
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Programming Methods for Multi-Level Flash Eeproms
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Active Termination Circuit and Method for Controlling the Impedance of External Integrated Circuit Terminals
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Active Termination Circuit and Method for Controlling the Impedance of External Integrated Circuit Terminals
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Method to Construct a Self Aligned Recess Gate for Dram Access Devices
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Zero latency-zero bus turnaround synchronous flash memory
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Memory Elements and Methods for Making Same
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Shallow Trench Isolation Using Low Dielectric Constant Insulator
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Metal Gate Engineering for Surface P-Channel Devices
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Method and Semiconductor Device Having Copper Interconnect for Bonding
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Memory Device Having Data Paths with Multiple Speeds
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Memory Device and Method Having Data Path with Multiple Prefetch I/O Configurations
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Backend Metallization Method and Device Obtained Therefrom
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Cam Memory Architecture and a Method of Forming and Operating a Device According to a Cam Memory Architecture
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Memory Device and Method Having Low-Power, High Write Latency Mode and High-Power, Low Write Latency Mode and/or Independently Selectable Write Latency
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Memory Device and Method Having Low-Power, High Write Latency Mode and High-Power, Low Write Latency Mode and/or Independently Selectable Write Latency
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Structure and Method of Fabricating a Transistor Having a Trench Gate
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Method of Electroplating a Substance Over a Semiconductor Substrate
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Memory device with chemical vapor deposition of titanium for titanium silicide contacts
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Method and Structure for Manufacturing Improved Yield Semiconductor Packaged Devices
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Atomic Layer Deposition Methods and Atomic Layer Deposition Tools
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Self-Aligned Silicide for Word Lines and Contacts
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Power Savings in Active Standby Mode
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Non-Contiguous Address Erasable Blocks and Command in Flash Memory
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Communication System, Interrogators and Communication Methods
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Permanent Memory Block Protection in a Flash Memory Device
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Digital Phase Mixers with Enhanced Speed
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Reduced Data Line Pre-Fetch Scheme
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Method and Apparatus Providing Cmos Imager Device Pixel with Transistor Having Lower Threshold Voltage Than Other Imager Device Transistors
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Output Impedance Calibration Circuit with Multiple Output Driver Models
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Memory System, Method and Predecoding Circuit Operable in Different Modes for Selectively Accessing Multiple Blocks of Memory Cells for Simultaneous Writing or Erasure
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Memory System, Method and Predecoding Circuit Operable in Different Modes for Selectively Accessing Multiple Blocks of Memory Cells for Simultaneous Writing or Erasure
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Memory System, Method and Predecoding Circuit Operable in Different Modes for Selectively Accessing Multiple Blocks of Memory Cells for Simultaneous Writing or Erasure
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Multiple Deposition for Integration of Spacers in Pitch Multiplication Process
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Pitch Reduced Patterns Relative to Photolithography Features
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Assemblies and Methods for Illuminating a Display
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Circuits and Methods of Temperature Compensation for Refresh Oscillator
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Circuits and Methods of Temperature Compensation for Refresh Oscillator
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Memory with Address Management
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Active Termination Control
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Active Termination Control
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Active Termination Control
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Programmable Dqs Preamble
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Formation of Standard Voltage Threshold and Low Voltage Threshold Mosfet Devices
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Active Termination Control
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Methods of Forming Openings, and Methods of Forming Container Capacitors
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Phase Splitter Using Digital Delay Locked Loops
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Anti-Reflective Coating Doped with Carbon for Use in Integrated Circuit Technology and Method of Formation
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Synchronous Flash Memory with Status Burst Output
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Active Termination Control Through Module Register
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Burst Counter Controller and Method in a Memory Device Operable in a 2-Bit Prefetch Mode
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Methods of Forming Transistors
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Adjustable Timing Circuit of an Integrated Circuit
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Atomic Layer Deposition Systems and Methods Including Silicon-Containing Tantalum Precursor Compounds
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Method and Circuit for Adjusting the Timing of Output Data Based on the Current and Future States of the Output Data
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Capacitor Layout Orientation
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Method and Apparatus for Converting Parallel Data to Serial Data in High Speed Applications
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Methods of Forming an Integrated Circuit Package
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Methods for Securing Packaged Semiconductor Devices to Carrier Substrates
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Method and System for Using Dynamic Random Access Memory as Cache Memory
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Structure and Method of Fabricating a Transistor Having a Trench Gate
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Mixed Enclave Operation in a Computer Network
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Memory Module and Method Having Improved Signal Routing Topology
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Layered Microlens Structures and Devices
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Method and Apparatus for Output Data Synchronization with System Clock in Ddr
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Battery-Powered Electronic Device with Spaced Contact Extensions
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Method and Apparatus for Controlling Reproduction of an Audiovisual Work
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Methods for Packaging Image Sensitive Electronic Devices
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Methods for Packaging Image Sensitive Electronic Devices
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Methods for Packaging Image Sensitive Electronic Devices
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Method and Circuit for Adjusting a Self-Refresh Rate to Maintain Dynamic Data at Low Supply Voltages
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Digital Delay-Locked Loop Circuits with Hierarchical Delay Adjustment
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Method of Forming Shallow Doped Junctions Having a Variable Profile Gradation of Dopants
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Methods of Forming Transistor Gates; and Methods of Forming Programmable Read-Only Memory Constructions
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Row Driven Imager Pixel
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Continuous Interleave Burst Access
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Interleaved Delay Line for Phase Locked and Delay Locked Loops
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Copper Interconnect for Semiconductor Device
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Copper Interconnect
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Longest Match Detection in a Cam
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Copper Interconnect
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Method of Addressing Messages and Communications System
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Selectable Clock Input
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System and Method for Locating Individuals and Equipment, Airline Reservation System, Communication System
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Methods of Forming a Plurality of Capacitor Devices
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Methods of Forming a Plurality of Capacitor Devices
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Measure Controlled Delay with Duty Cycle Control
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Method and Apparatus for Electronic Image Processing
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Delay Line Synchronizer Apparatus and Method
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Method for Fabricating Packaged Die
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Memory Device and Method Having Data Path with Multiple Prefetch I/O Configurations
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Radio Frequency Data Communications Device
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Status Register to Improve Initialization of a Synchronous Memory
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Method and Apparatus for Controlling Refresh Operations in a Dynamic Memory Device
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Dynamically Setting Burst Length of Memory Device by Applying Signal to at Least One External Pin During a Read or Write Transaction
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System and Method for Power Saving Delay Locked Loop Control by Selectively Locking Delay Interval
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Methods and Apparatuses for Analyzing and Controlling Performance Parameters in Mechanical and Chemical-Mechanical Planarization of Microelectronic Substrates
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Synchronous Memory Open Page Register
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Methods of Forming an Rfid Device Including a Substrate Containing an Integrated Circuit
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System and Method for Providing Temperature Data from a Memory Device Having a Temperature Sensor
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Applying Epitaxial Silicon in Disposable Spacer Flow
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Wireless communication devices and methods of forming and operating the same
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Generating Multi-Phase Clock Signals Using Hierarchical Delays
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Method and Apparatus Providing Cmos Imager Device Pixel with Transistor Having Lower Threshold Voltage Than Other Imager Device Transistors
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High Selectivity Bpsg to Teos Etchant
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Portable Computer Supporting Paging Instructions
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Temperature Sensing Device in an Integrated Circuit
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Atomic Layer Deposition Methods
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Multiple Level Cell Memory Device with Single Bit Per Cell, Re-Mappable Memory Block
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Memory Modules Having a Memory Hub Containing a Posted Write Buffer, a Memory Device Interface and a Link Interface, and Method of Posting Write Requests in Memory Modules
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Multiple Level Programming in a Non-Volatile Memory Device
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Cam Modified to Be Used for Statistic Calculation in Network Switches and Routers
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Flip-Chip Adaptor Package for Bare Die
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Stackable Ball Grid Array Package
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Method for Forming Sublithographic Features During the Manufacture of a Semiconductor Device and a Resulting in-Process Apparatus
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Fast and Compact Circuit for Bus Inversion
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256 Meg Dynamic Random Access Memory
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256 Meg Dynamic Random Access Memory
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Multiple Level Programming in a Non-Volatile Memory Device
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Conductive Container Structures Having a Dielectric Cap
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Memory Device and Method Having Multiple Internal Data Buses and Memory Bank Interleaving
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Circuit and Method for Operating a Delay-Lock Loop in a Power Saving Manner
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Radio Frequency Identification (Rfid) Tags and Methods of Communicating Between a Radio Frequency Identification (Rfid) Tag and an Interrogator
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Centralizing the Lock Point of a Synchronous Circuit
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Clock Capture in Clock Synchronization Circuitry
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Clock Capture in Clock Synchronization Circuitry
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Clock Capture in Clock Synchronization Circuitry
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Clock Capture in Clock Synchronization Circuitry
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Semiconductor Fabrication Using a Collar
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Method for Integrated Circuit Fabrication Using Pitch Multiplication
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Computer System Having Apparatus for Generating a Delayed Clock Signal
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Methods for Generating a Delayed Clock Signal
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Apparatus and Method for Generating a Delayed Clock Signal
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Apparatus and Method for Managing Voltage Buses
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Small Electrode for a Chalcogenide Switching Device and Method for Fabricating Same
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Method and Architecture to Calibrate Read Operatons in Synchronous Flash Memory
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Wireless Communication Systems, Interrogators and Methods of Communicating Within a Wireless Communication System
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Memory Modules Having Accurate Operating Parameters Stored Thereon and Methods for Fabricating and Implementing Such Devices
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Method for Forming Rfid Devices and Tagged Objects Including Substrates Having Integrated Circuits Mounted Thereon
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Synchronization Devices Having Input/Output Delay Model Tuning Elements in Signal Paths to Provide Tuning Capabilities to Offset Signal Mismatch
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Programming Methods for Multi-Level Memory Devices
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Structures with Increased Photo-Alignment Margins
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User Configurable Commands for Flash Memory
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User Configurable Commands for Flash Memory
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Devices and Methods for Controlling a Slew Rate of a Signal Line
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Methods for Increasing Photo-Alignment Margins
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Method for Fabricating Semiconductor Components with Thinned Substrate, Circuit Side Contacts, Conductive Vias and Backside Contacts
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Systems and Methods for Managing Data Stored in a Multi-Drive Storage Device
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Non-Volatile Memory Device with Both Single and Multiple Level Cells
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Phase Shifters, Interrogators, Methods of Shifting a Phase Angle of a Signal, and Methods of Operating an Interrogator
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Data Security for Digital Data Storage
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Phase Detector and Method Having Hysteresis Characteristics
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Circuit and Method for Controlling a Clock Synchronizing Circuit for Low Power Refresh Operation
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Memory Hub and Access Method Having Internal Prefetch Buffers
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Methods of Operating Electronic Devices, and Methods of Providing Electronic Devices
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Layered Microlens Structures Having Upper and Lower Lenses and Devices Including the Same
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System and Memory for Sequential Multi-Plane Page Memory Operations
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Power Savings in Active Standby Mode
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Electronic Communication Devices, Methods of Forming Electrical Communication Devices, and Communications Methods
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Method for Assisting Video Compression in a Computer System
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Data Security for Digital Data Storage
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Pinned Photodiode Photodetector with Common Buffer Transistor and Binning Capability
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Anti-theft system and apparatus and method for selectively disabling/enabling electrical apparatus
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Top/Bottom Symmetrical Protection Scheme for Flash
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System and Method for Mode Register Control of Data Bus Operating Mode and Impedance
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Multiple Processor System and Method Including Multiple Memory Hub Modules
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Mis Capacitor and Method of Formation
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Programming Memory Devices
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Formation of Standard Voltage Threshold and Low Voltage Threshold Mosfet Devices
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Formation of Standard Voltage Threshold and Low Voltage Threshold Mosfet Devices
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Method and System for Rfid Communication
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Method of manufacturing an integrated circuit and photosensor cell with selectively silicided gates
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Diagnostic and Managing Distributed Processor System
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Apparatus and Method for Independent Control of on-Die Termination for Output Buffers of a Memory Device
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Memory Hub with Internal Cache and/or Memory Access Prediction
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Memory Devices with Buffered Command Address Bus
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Memory System and Method Having Uni-Directional Data Buses
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Method and System for Using Dynamic Random Access Memory as Cache Memory
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Memory Device and Method Having Data Path with Multiple Prefetch I/O Configurations
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Tracking Systems, Passive Rfids, Methods of Locating and Identifying Rfids, and Methods of Tracking Items
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Low Power Chip Select (Cs) Latency Option
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Wake Up Device for Communications System
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Method and Apparatus for Pixel Signal Binning and Interpolation in Column Circuits of a Sensor Circuit
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System and Method for Identifying a Radio Frequency Identification (Rfid) Device
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Rfid Communication Systems and Methods, and Rfid Readers and Systems
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Methods and Apparatus for Electromechanically and/or Electrochemically-Mechanically Removing Conductive Material from a Microelectronic Substrate
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Multiple Deposition for Integration of Spacers in Pitch Multiplication Process
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Dynamic Synchronization of Data Capture on an Optical or Other High Speed Communications Link
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Ddr Ii Write Data Capture Calibration
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Row Driver for Selectively Supplying Operating Power to Imager Pixel
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Methods of Fabrication of Package Assemblies for Optically Interactive Electronic Devices and Package Assemblies Therefor
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Generating Multi-Phase Clock Signals Using Hierarchical Delays
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Electronic Monitoring Systems, Shipment Container Monitoring Systems and Methods of Monitoring a Shipment in a Container
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Flash Memory Programming to Reduce Program Disturb
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Through-Hole Contacts in a Semiconductor Device
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Pitch Reduced Patterns Relative to Photolithography Features
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Semiconductor Component Having Plate, Stacked Dice and Conductive Vias
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Flash with Consistent Latency for Read Operations
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RFIDS, interrogators, indication systems, methods of determining a bi-directional communication range of an interrogator, methods of activating an observable indicator, and methods of indicating bi-directional functionality of a radio connection
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Co-Sputter Deposition of Metal-Doped Chalcogenides
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In-Situ Chemical-Mechanical Planarization Pad Metrology Using Ultrasonic Imaging
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Method of Forming a Recessed Gate Structure on a Substrate Having Insulating Columns and Removing Said Insulating Columns After Forming a Conductive Region of the Gate Structure
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Method for Low Power Refresh of a Dynamic Random Access Memory Using a Slower Refresh Rate Than a Normal Refresh Rate
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Memory Hub and Method for Memory System Performance Monitoring
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Automated Antenna Trim for Transmitting and Receiving Semiconductor Devices
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Devices and Methods for Controlling a Slew Rate of a Signal Line
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Multiple Level Cell Memory Device with Single Bit Per Cell, Re-Mappable Memory Block
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Low Power and Low Timing Jitter Phase-Lock Loop and Method
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Active Pixel Sensor with a Diagonal Active Area
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Cmos Imager with Selectively Silicided Gates
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Thin Film Structure That May Be Used with an Adhesion Layer
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Non-Skipping Auto-Refresh in a Dram
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Read Command Triggered Synchronization Circuitry
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Methods and Systems of Rfid Tags Using Rfid Circuits and Antennas Having Unmatched Frequency Ranges
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Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Programming the Same
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Method and System for Improved Efficiency of Synchronous Mirror Delays and Delay Locked Loops
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Methods and Systems of Using Radio Frequency Identification Tags
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Capacitive Multidrop Bus Compensation
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Method for Writing to Multiple Banks of a Memory Device
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Method for an Integrated Circuit Contact
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Wake Up Device for Communications System and Methods
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Wake Up Device for Communications System
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Non-Volatile Memory Structure
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Wireless Communications Devices
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Secure Cargo Transportation System
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Secure Cargo Transportation System
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Methods and Aparatuses for Radio Frequency Identification {Rfid) Tags Configured to Allow Antenna Trim
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System and Method for Locating Individuals and Equipment, Airline Reservation System, Communication System
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System and Method for Locating Individuals and Equipment, Airline Reservation System, Communication System
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System and Method for Locating Individuals and Equipment, Airline Reservation System, Communication System
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Phase Shifters, Interrogators, Methods of Shifting a Phase Angle of a Signal, and Methods of Operating an Interrogator
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Radio Frequency Identification Apparatuses
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Method and Apparatus for Wireless Communication of Identification Information Between Radio Frequency Devices
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Methods and Systems of Using Rfid Tags in Emergency Situations
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Electronic Communication Devices, Methods of Forming Electrical Communication Devices, and Communications Methods
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Anti-Theft System and Apparatus and Method for Selectively Disabling/Enabling Electrical Apparatus
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Methods and Systems Using Polarization Modulated Electromagnetic Waves
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Radio Frequency Identification Sensor Tag Apparatuses
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Systems for Remotely Maintaining Inventory
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Remote Communication Devices, Radio Frequency Identification Devices, Wireless Communication Systems, Wireless Communication Methods, Radio Frequency Identification Device Communication Methods, and Methods of Forming a Remote Communication Device
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Wireless Communication Systems, Interrogators and Methods of Communicating Within a Wireless Communication System
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Systems Utilizing an Interrogator and One or More RFID Tags
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Methods of Operating Electronic Devices, and Methods of Providing Electronic Devices
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Methods and Apparatus for Rfid Tag Communications
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Backscatter interrogators, communication systems and backscatter communication methods
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Backscatter interrogators, communication systems and backscatter communication methods
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Radio Frequency Identification Devices, Remote Communication Devices, Identification Systems, Communication Methods, and Identification Methods
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Radio Frequency Identification Devices, Remote Communication Devices, Identification Systems, Communication Methods, and Identification Methods
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Radio Frequency Identification Devices, Remote Communication Devices, Identification Systems, Communication Methods, and Identification Methods
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RF Identification System with Restricted Range
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RF Identification System with Restricted Range
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RF Identification System with Restricted Range
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Radio Frequency Identification Device and Method
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Radio Frequency Identification Device and Method
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Miniature Radio Frequency Transceiver
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Selectively Coupling to Feed Points of an Antenna System
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Rfid Tags and Systems
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Wireless Communication Systems, Interrogators and Methods of Communicating Within a Wireless Communication System
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Thin Profile Battery Bonding Method, Method Of Conductively Interconnecting Electronic Components, Battery Powerable Apparatus, Radio Frequency Communication Device, And Electric Circuit
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Wireless Identification Device, RFID Device with Push-on/Push-off Switch, and Method of Manufacturing Wireless Identification Device
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Wireless Identification Device, RFID Device With Push-on/Push-off Switch, and Method of Manufacturing Wireless Identification Device
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Wireless Identification Device, RFID Device With Push-on/Push-off Switch, and Method of Manufacturing Wireless Identification Device
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Method of Addressing Messages and Communications System
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Enhanced Atomic Layer Deposition
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Wireless Communication Systems, Interfacing Devices, Communication Methods, Methods of Interfacing With an Interrogator, and Methods of Operating an Interrogator
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Wireless Communication Systems, Interfacing Devices, Communication Methods, Methods of Interfacing With an Interrogator, and Methods of Operating an Interrogator
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Wireless Communication Systems and Methods
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Wireless Communication Systems, Interfacing Devices, Communication Methods, Methods of Interfacing With an Interrogator, and Methods of Operating an Interrogator
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Method of Addressing Messages and Communications Systems
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Cimmunications systems for radio frequency identification (RFID)
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Small Electrode for Phase Change Memories
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Methods for Forming Integrated Circuits Within Substrates
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Methods for Forming Integrated Circuits Within Substrates
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Method of Addressing Messages and Communications System
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Method of Addressing Messages and Communications
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Method of Addressing Messages and Communications System
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Packaged Microelectronic Imagers and Methods of Packaging Microelectronic Imagers
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Method and Apparatus for Rfid Communication
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Method and Apparatus for Rfid Communication
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Method and Apparatus for RFID Communication
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Method of Addressing Messages, Method of Establishing Wireless Communications, and Communications System
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Method and Apparatus to Manage Rfid Tags
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Method and System to Determine Physical Parameters as Between a Rfid Tag and a Reader
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Methods for Electronic Tracking of Units Associated with a Batch
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Methods for Electronic Tracking of Units Originating from a Common Source
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Balanced Data Bus Inversion
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Formation of Standard Voltage Threshold and Low Voltage Threshold Mosfet Devices
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Automating the Process of Puchasing a Memory Upgrade for a Computer System
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System and Memory for Sequential Multi-Plane Page Memory Operations
Patent: 7,580,283 →
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Publication: US 2008/0056026
Rfid Label Time Synchronization
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Publication: US 2009/0109041
Small Electrode for a Chalcogenide Switching Device and Method for Fabricating Same
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Memory Array Having Floating Gate Semiconductor Device
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Apparatus and Method for Packaging Circuits
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Rfid Device Time Synchronization from a Public Source
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Publication: US 2009/0128292
Wireless Device with an Rfid Interrogator
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Wrapping with Antenna
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Radio Frequency Identification Device Operating Methods, Radio Frequency Identification Device Configuration Methods, and Radio Frequency Identification Devices
Patent: 8,624,711 →
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Memory Module and Method Having Improved Signal Routing Topology
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Radio Frequency Communications Devics
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Publication: US 2008/0211636
Memory Device and Method Having Data Path with Multiple Prefetch I/O Configurations
Patent: 7,457,172 →
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Method of Timing Calibration Using Slower Data Rate Pattern
Patent: 7,721,135 →
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Publication: US 2008/0098253
Multiple Processor System and Method Including Multiple Memory Hub Modules
Patent: 7,581,055 →
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Publication: US 2008/0215792
Memory Device and Method Having Programmable Address Configurations
Patent: 7,564,733 →
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Publication: US 2008/0175090
Applying Epitaxial Silicon in Disposable Spacer Flow
Patent: 7,884,427 →
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Publication: US 2008/0128820
RFID System and Method for Wirelessly Interfacing With an Interrogator
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Publication: US 2008/0117025
Power Estimation of an Active RFID Device
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Publication: US 2009/0195356
Programming Memory Devices
Patent: 7,505,323 →
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Publication: US 2008/0130373
Multi-Chip Stacked Devices
Application: 12/030,045 →
Configurable Inputs and Outputs for Memory Stacking System and Method
Patent: 7,602,630 →
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Publication: US 2008/0137439
Structure and Method of Fabricating a Transistor Having a Trench Gate
Patent: 7,879,665 →
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Publication: US 2008/0200005
Method and Apparatus for Converting Parallel Data to Serial Data in High Speed Applications
Patent: 7,525,458 →
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Publication: US 2008/0136690
Methods and Apparatuses to Secure Data Transmission in RFID Systems Against Eavesdropping
Application: 12/037,646 →
Publication: US 2009/0214037
Anti-Theft Method for Detecting the Unauthorized Opening of Containers and Baggage
Patent: 43,415 →
Application: 12/038,473 →
Multiple Deposition for Integration of Spacers in Pitch Multiplication Process
Patent: 8,123,968 →
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Publication: US 2008/0149593
Methods and Apparatuses to Secure Data Transmission in Rfid Systems
Patent: 8,174,362 →
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Publication: US 2009/0224884
Method and System to Determine Physical Parameters as Between an Rfid Tag and a Reader
Patent: 7,944,356 →
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Publication: US 2009/0091428
Anti-Theft Method for Detecting the Unauthorized Opening of Containers and Baggage
Patent: 42,777 →
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Split Embedded DRAM Processor
Patent: 8,489,861 →
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Publication: US 2008/0180450
Reconfigurable Memory Module and Method
Patent: 7,818,712 →
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Publication: US 2008/0140952
Method and System for Using Dynamic Random Access Memory as Cache Memory
Patent: 7,917,692 →
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Publication: US 2008/0177943
Memory Hub and Method for Memory System Performance Monitoring
Patent: 7,533,213 →
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Publication: US 2008/0140904
Apparatus and Methods for Optically-Coupled Memory Systems
Patent: 7,613,026 →
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Publication: US 2008/0158931
System and Method for Memory Hub-Based Expansion Bus
Patent: 7,610,430 →
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Publication: US 2008/0222379
Method and Apparatus Providing Cmos Imager Device Pixel with Transistor Having Lower Threshold Voltage Than Other Imager Device Transistors
Patent: 7,791,114 →
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Publication: US 2008/0176350
Full-scene anti-aliasing method and system
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Publication: US 2008/0186329
Fast hop frequency hopping protocol
Application: 12/103,291 →
Publication: US 2009/0257474
RFID Fast Hop Frequency Hopping
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Publication: US 2009/0257473
Method and Apparatus for Generating Expect Data from a Captured Bit Pattern, and Memory Device Using Same
Patent: 7,657,813 →
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User Configurable Commands for Flash Memory
Patent: 7,551,481 →
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Publication: US 2008/0192547
Apparatus and Method for Direct Memory Access in a Hub-Based Memory System
Patent: 7,966,430 →
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Publication: US 2009/0327532
High Selectivity Bpsg to Teos Etchant
Patent: 7,977,251 →
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Publication: US 2008/0233759
Computer with Rfid Interrogator
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Publication: US 2009/0273448
Item Identification Using RFID
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Publication: US 2009/0273453
Power Conserving Active RFID Label
Patent: 8,400,297 →
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Publication: US 2009/0273473
Rfid Interrogator with Adjustable Signal Characteristics
Patent: 8,179,232 →
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Rfid Devices Using Rfid Circuits and Antennas Having Unmatched Frequency Ranges
Patent: 7,852,221 →
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Publication: US 2009/0278688
Structures Including Passivated Germanium
Patent: 7,915,712 →
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Publication: US 2008/0237802
Flexible RFID Label
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Publication: US 2009/0284377
Method for Adjusting Feature Size and Position
Patent: 8,703,616 →
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Publication: US 2008/0254627
Memory System and Method for Improved Utilization of Read and Write Bandwidth of a Graphics Processing System
Patent: 7,724,262 →
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Publication: US 2008/0218525
Multiple Level Programming in a Non-Volatile Memory Device
Patent: 8,045,392 →
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Publication: US 2008/0219055
Multi-Function Floating Point Arithmetic Pipeline
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Publication: US 2008/0263122
Distributed Write Data Drivers for Burst Access Memories
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Analog RFID System
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Publication: US 2009/0315683
Method of Forming a Structure Over a Semiconductor Substrate
Patent: 7,803,678 →
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Publication: US 2008/0261388
Semiconductor Device with Self Refresh Test Mode
Patent: 8,687,446 →
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Publication: US 2008/0279022
Method and Apparatus for Generating a Phase Dependent Control Signal
Patent: 7,602,876 →
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Publication: US 2008/0279323
Memory Hub and Access Method Having Internal Prefetch Buffers
Patent: 8,127,081 →
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Publication: US 2009/0187714
Layout for High Density Conductive Interconnects
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Publication: US 2008/0290374
Memory Device Having Data Paths with Multiple Speeds
Patent: 7,817,482 →
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Publication: US 2008/0316841
System and Method for Power Saving Delay Locked Loop Control
Patent: 7,814,362 →
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Publication: US 2009/0006880
Bond Pad Rerouting Element, Rerouted Semiconductor Devices Including the Rerouting Element, and Assemblies Including the Rerouted Semiconductor Devices
Patent: 7,851,922 →
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Publication: US 2009/0008797
Method and System for Improved Efficiency of Synchronous Mirror Delays and Delay Locked Loops
Patent: 7,688,653 →
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Publication: US 2009/0021290
Multiple Level Cell Memory Device with Single Bit Per Cell, Re-Mappable Memory Block
Patent: 8,009,469 →
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Publication: US 2009/0027962
Low Power and Low Timing Jitter Phase-Lock Loop and Method
Patent: 7,728,637 →
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Publication: US 2009/0039928
Read Command Triggered Synchronization Circuitry
Patent: 7,593,287 →
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Publication: US 2009/0097340
Chemical Vapor Deposition of Titanium
Patent: 8,456,007 →
Application: 12/249,774 →
Publication: US 2009/0039517
System and Method for Providing Temperature Data from a Memory Device Having a Temperature Sensor
Patent: 7,677,796 →
Application: 12/256,315 →
Publication: US 2009/0052268
Capacitive Multidrop Bus Compensation
Patent: 7,913,005 →
Application: 12/263,681 →
Publication: US 2009/0070503
Memory Device and Method Having Low-Power, High Write Latency Mode and High-Power, Low Write Latency Mode and/or Independently Selectable Write Latency
Patent: 7,826,283 →
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Publication: US 2009/0067267
Low Current Wide Vref Range Input Buffer
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Publication: US 2009/0085613
Systems and Methods for Performing a Hot Input Function
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Publication: US 2009/0100208
A Method for Measuring a Temperature in an Electronic Device Having a Battery
Patent: 7,821,235 →
Application: 12/273,626 →
Publication: US 2009/0072795
Method and Apparatus for Providing Illumination with a Pulse-Controlled Light Emitting Diode Source
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Publication: US 2009/0140660
Circuit and Method for Reducing Power in a Memory Device During Standby Modes
Patent: 7,729,192 →
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Publication: US 2009/0080278
Method and Circuit for Off Chip Driver Control, and Memory Device Using Same
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Publication: US 2009/0091350
System and Method for on-Board Diagnostics of Memory Modules
Patent: 7,913,122 →
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Publication: US 2009/0106591
Memory Hub with Internal Cache and/or Memory Access Prediction
Patent: 7,945,737 →
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Publication: US 2009/0125688
Small Electrode for Phase Change Memories
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Publication: US 2009/0121212
Memory Hub with Integrated Non-Volatile Memory
Patent: 7,975,122 →
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Publication: US 2009/0132781
Contoured Surface Cover Plate for Image Sensor Array
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Publication: US 2009/0141160
Techniques for Configuring Memory Systems Using Accurate Operating Parameters
Patent: 7,684,276 →
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Publication: US 2009/0147609
Fast and Compact Circuit for Bus Inversion
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Publication: US 2009/0177825
Programming Memory Devices
Patent: 7,688,630 →
Application: 12/370,810 →
Publication: US 2009/0154247
Balanced Data Bus Inversion
Patent: 7,701,368 →
Application: 12/371,697 →
Publication: US 2009/0179782
256 Meg Dynamic Random Access Memory
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Publication: US 2009/0245009
Memory Devices Having Contact Features
Patent: 8,076,783 →
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Publication: US 2009/0152737
Atomic Layer Deposition Systems and Methods Including Silicon-Containing Tantalum Precursor Compounds
Patent: 7,943,507 →
Application: 12/409,139 →
Publication: US 2009/0215262
Pinned Photodiode Photodetector with Common Pixel Transistors and Binning Capability
Patent: 42,292 →
Application: 12/413,626 →
Non-Volatile Memory Device with Both Single and Multiple Level Cells
Patent: 7,808,822 →
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Publication: US 2009/0190400
Constructions Comprising Hafnium Oxide and/or Zirconium Oxide
Patent: 8,049,304 →
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Publication: US 2009/0195967
Output Impedance Calibration Circuit with Multiple Output Driver Models
Patent: 8,049,530 →
Application: 12/424,684 →
Publication: US 2009/0201047
Parallel-To-Serial Data Sort Device
Patent: 7,764,206 →
Application: 12/427,577 →
Publication: US 2009/0201746
Apparatus for Writing to Mutiple Banks of a Memory Device
Patent: 7,869,301 →
Application: 12/462,433 →
Publication: US 2009/0296512
Apparatus, Method, and Product for Downscaling an Image
Patent: 8,194,098 →
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Publication: US 2009/0225101
Memory Module and Method Having Improved Signal Routing Topology
Patent: 7,746,095 →
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Publication: US 2009/0243649
Method of Orperating a Cmos Aps Pixel Sensor
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Single Poly Cmos Imager
Patent: 8,003,506 →
Application: 12/492,765 →
Publication: US 2009/0298272
Method of Addressing Messages and Communications Systems
Patent: 43,254 →
Application: 12/493,542 →
Methods and Systems of Attaching a Radio Transceiver to an Antenna
Patent: 8,432,284 →
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Publication: US 2009/0266896
Dynamically Setting Burst Length of Double Data Rate Memory Device by Applying Signal to at Least One External Pin During a Read or Write Transaction
Patent: 8,019,913 →
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Publication: US 2009/0276548
Method and System for Facilitating Purchase Transactions Across a Network
Patent: 7,904,387 →
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Publication: US 2009/0281916
Multiple Processor System and Method Including Multiple Memory Hub Modules
Patent: 7,873,775 →
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Publication: US 2009/0282182
A Semiconductor Device and Method of Fabrication Thereof
Patent: 8,049,342 →
Application: 12/510,045 →
Publication: US 2009/0286356
Formation of Standard Voltage Threshold and Low Voltage Threshold Mosfet Devices
Patent: 7,755,146 →
Application: 12/512,631 →
Publication: US 2009/0286366
Methods of Forming Integrated Circuit Devices
Patent: 7,915,136 →
Application: 12/512,756 →
Publication: US 2009/0286377
System and Memory for Sequential Multi-Plane Page Memory Operations
Patent: 8,050,131 →
Application: 12/534,586 →
Publication: US 2010/0008144
Apparatus and Method for Reducing Removal Forces for Cmp Pads
Patent: 8,308,528 →
Application: 12/535,445 →
Publication: US 2009/0298395
Method of Addressing Messages and Communications System
Patent: 42,599 →
Application: 12/541,882 →
Read Command Triggered Synchronization Circuitry
Patent: 7,969,814 →
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Publication: US 2010/0027368
Semiconductor Device Having Copper Interconnect for Bonding
Patent: 8,759,970 →
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Publication: US 2009/0309222
Method of Addressing Messages and Communications System
Patent: 7,936,706 →
Application: 12/556,530 →
Publication: US 2009/0322491
Methods and Apparatus for Electromechanically and/or Electrochemically-Mechanically Removing Conductive Material from a Microelectronic Substrate
Patent: 7,972,485 →
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Publication: US 2010/0006428
Method and Apparatus for Generating a Phase Dependent Control Signal
Patent: 8,107,580 →
Application: 12/562,709 →
Publication: US 2010/0007383
Method for an Integrated Circuit Contact
Patent: 8,097,514 →
Application: 12/565,280 →
Publication: US 2010/0019388
Circuit and Method for Controlling a Clock Synchronizing Circuit for Low Power Refresh Operation
Patent: 7,983,110 →
Application: 12/568,507 →
Publication: US 2010/0014371
Delay Line Synchronizer Apparatus and Method
Patent: 8,164,375 →
Application: 12/568,525 →
Publication: US 2010/0019822
Method for Generating a Clock Signal
Patent: 8,127,171 →
Application: 12/568,532 →
Publication: US 2010/0023793
Method for Assisting Video Compression in a Computer System
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Publication: US 2010/0020247
Radio Frequency Identification Devices, Remote Communication Devices, Identification Systems, Communication Methods, and Identification Methods
Patent: 8,004,407 →
Application: 12/569,791 →
Publication: US 2010/0013637
Synchronous Flash Memory with Status Burst Output
Patent: 8,010,767 →
Application: 12/570,570 →
Publication: US 2010/0088484
System and Method to Improve the Efficiency of Synchronous Mirror Delays and Delay Locked Loops
Patent: 8,212,595 →
Application: 12/574,847 →
Publication: US 2010/0026351
Apparatus and Methods for Optically-Coupled Memory Systems
Patent: 8,040,711 →
Application: 12/577,015 →
Publication: US 2010/0027310
System and Method for Memory Hub-Based Expansion Bus
Patent: 7,899,969 →
Application: 12/580,085 →
Publication: US 2010/0036989
Method for Selectively Removing Conductive Material from a Microelectronic Substrate
Patent: 8,048,287 →
Application: 12/580,941 →
Publication: US 2010/0032314
Method of Addressing Messages, Method of Establishing Wireless Communications, and Communications System
Application: 12/604,329 →
Electronic Device Package with an Optical Device
Patent: 8,097,895 →
Application: 12/615,943 →
Publication: US 2010/0052086
Multi-Chip Module and Methods
Patent: 8,048,715 →
Application: 12/616,526 →
Publication: US 2010/0055837
Method and System for Updating a Search Engine
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Application: 12/616,668 →
Publication: US 2010/0057802
Methods and Apparatus for Rendering or Preparing Digital Objects or Portions Thereof for Subsequent Processing
Patent: 7,978,193 →
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Publication: US 2010/0053157
Assemblies and Methods for Illuminating a Display
Patent: 7,999,885 →
Application: 12/623,564 →
Publication: US 2010/0066940
Electronic Monitoring Systems, Shipment Container Monitoring Systems and Methods of Monitoring a Shipment in a Container
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Application: 12/631,643 →
Publication: US 2010/0073139
Related Assignments (1)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 26, 2010
From: KEYSTONE TECHNOLOGY SOLUTIONS, LLC
To: MICRON TECHNOLOGY, INC.
Reel/Frame 023839/0881 →