Method of forming shallow doped junctions having a variable profile gradation of dopants
Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.
1. A method of forming an electrical structure on a substrate, the method comprising:
performing a first plasma doping (PLAD) operation to form a first doped region in a substrate; and
performing a second doping operation, the second doping operation comprising depositing dopants in the first doped region and in a second doped region that is contiguous with and extends below the first doped region, wherein the first doped region has a higher dopant concentration than the second doped region, the second doped region having a lower periphery that is substantially planar and substantially parallel to a top surface of the substrate.
2. The method as defined in claim 1 , wherein performing a first PLAD operation to form a first doped region in a substrate comprises performing the first PLAD operation to form the first doped region having a dopant concentration that terminates relatively abruptly at an uneven lower periphery.
3. The method as defined in claim 1 , wherein:
performing a first PLAD operation to form a first doped region in a substrate comprises forming the first doped region having a lower periphery at a depth of less than about 1000 Å; and
performing a second doping operation comprises forming the second doped region having a lower periphery at a depth that is less than about 1750 Åfrom the top surface of the substrate and at least about 250 Å greater than the depth of the lower periphery of the first doped region.
4. The method as defined in claim 1 , further comprising annealing the substrate after at least one of the second doping operation and the first PLAD operation to cause a more uniform distribution of dopants.
5. The method as defined in claim 4 , wherein annealing the substrate comprises rapid thermal annealing of the substrate.
6. The method as defined in claim 1 , wherein:
performing a first PLAD operation to form a first doped region in a substrate comprises conducting the first PLAD operation at an energy in a range of from about 5 KeV to about 15 KeV such that the first doped region has a dopant concentration in a range of from about 1×10 19 dopant atoms/cm 3 to about 5×10 21 dopant atoms/cm 3 ; and
performing a second doping operation comprises performing the second doping operation at an energy in a range of from about 10 KeV to about 25 KeV such that the second doped region has a dopant concentration in a range of from about 1×10 16 dopant atoms/cm 3 to about 1×10 19 dopant atoms/cm 3 , the second doping operation being conducted in a medium power implanter operating in a range of from about 0 KeV to about 200 KeV.
7. The method as defined in claim 1 , further comprising forming a portion of an electrical device that is selected from the group consisting of a diode, a resistor, and a transistor with the first doped region and the second doped region.
8. A method of forming an electrical structure on a substrate, the method comprising:
providing a gate region over a substrate, the gate region having a bottom surface;
performing a first plasma doping (PLAD) operation to form a first doped region in the substrate, wherein the first doped region does not underlap the bottom surface of the gate region; and
performing a second doping operation, the second doping operation comprising depositing dopants in the first doped region and in a second doped region that is contiguous with and extends below the first doped region, wherein the first doped region has a higher dopant concentration than the second doped region, the second doped region having at least a portion thereof that underlaps the bottom surface of the gate region.
9. The method as defined in claim 8 , wherein performing a first PLAD operation to form a first doped region in the substrate comprises forming the first doped region having a dopant concentration that terminates relatively abruptly at an uneven lower periphery.
10. The method as defined in claim 8 , wherein:
performing a first PLAD operation to form a first doped region in the substrate comprises forming the first doped region having a lower periphery at a depth of less than about 1000 Å; and
performing a second doping operation comprises forming the second doped region having a lower periphery at a depth that is less than about 1750 Å from a top surface of the substrate and at least about 250 Å greater than the depth of the lower periphery of the first doped region.
11. The method as defined in claim 8 , further comprising annealing the substrate after at least one of the second doping operation and the first PLAD operation to cause a more uniform distribution of dopant.
12. The method as defined in claim 11 , wherein annealing the substrate comprises performing the annealing as a rapid thermal anneal.
13. The method as defined in claim 8 , wherein:
performing a first PLAD operation to form a first doped region in the substrate comprises conducting the first PLAD operation at an energy in a range of from about 5 KeV to about 15 KeV such that the first doped region has a dopant concentration in a range of from about 1×10 19 dopant atoms/cm 3 to about 5×10 21 dopant atoms/cm 3 ; and
performing a second doping operation comprises performing the second doping operation at an energy in a range of from about 10 KeV to about 25 KeV such that the second doped region has a dopant concentration in a range of from about 1×10 16 dopant atoms/cm 3 to about 1×10 19 dopant atoms/cm 3 , the second doping operation being conducted in a medium power implanter operating in a range from about 0 KeV to about 200 KeV.
14. The method as defined in claim 8 , further comprising forming a portion of an electrical device that is a transistor from the first doped region and the second doped region.